Cited by 66Advanced Memory and Neural ComputingFerroelectric and Negative Capacitance DevicesNeural Networks and Applications

A memristive deep belief neural network based on silicon synapses

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Wang, Wei, Danial, Loai, Li, Yang, Herbelin, Eric, Pikhay, Evgeny, Roizin, Yakov, Hoffer, Barak, Wang, Zhongrui +1 more·2022·Nature Electronics

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Crossref · 10.1038/s41928-022-00878-9

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  • Various studies have demonstrated that the energy efficiency, hardware size, and inference speed of memristor crossbar arrays can be effectively improved compared with conventional CMOS-based processors.

    “Based on the desirable characteristics of the memristor crossbar array, various studies have demonstrated that the energy efficiency, hardware size, and inference speed can be effectively improved compared with the conventional CMOS-based processors 12,17,18”

    From Linear conductance update improvement of CMOS-compatible second-order memristors for fast and energy-efficient training of a neural network using a memristor crossbar array (2023) · cites this paper as [17]

    The Memristive synaptic array section (p. 5) reports estimated improvements in energy efficiency and performance density for array operations compared with a Tesla V100 GPU. The Methods (p. 15) say these estimates exclude peripheral-circuit energy and footprint. Performance density is not a direct comparison of total hardware size, and the paper does not establish improved inference speed over a conventional CMOS processor. (LLM, conf=0.88)

    Experimental — accuracy not yet measured

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Research works printed but not linked: 17

  1. [7]7. Chen, P.-Y., Peng, X. & Yu, S. NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures. in 2017 IEEE International Electron Devices Meeting (IEDM) 6.1.1-6.1.4 (IEEE, 2017). doi:10.1109/IEDM.2017.8268337. · DOI
  2. [8]8. Cheng, H. Y. et al. An ultra high endurance and thermally stable selector based on TeAsGeSiSe chalcogenides compatible with BEOL IC Integration for cross-point PCM. in 2017 IEEE International Electron Devices Meeting (IEDM) 2.2.1-2.2.4 (IEEE, 2017). doi:10.1109/IEDM.2017.8268310. · DOI
  3. [9]9. Chang, C. C. et al. Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse. IEEE J. Emerg. Sel. Top. Circuits Syst. 8 , 116-124 (2018).
  4. [10]10. Wang, C. et al. Scalable massively parallel computing using continuous-time data representation in nanoscale crossbar array. Nat. Nanotechnol. (2021) doi:10.1038/s41565021-00943-y. · DOI
  5. [20]20. Yang, J. et al. Artificial Synapses Emulated by an Electrolyte-Gated Tungsten-Oxide Transistor. Adv. Mater. 1801548 (2018) doi:10.1002/adma.201801548. · DOI
  6. [25]25. Song, L., Qian, X., Li, H. & Chen, Y. PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning. in 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA) 541-552 (IEEE, 2017). doi:10.1109/HPCA.2017.55. · DOI
  7. [26]26. Shafiee, A. et al. ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. in Annual International Symposium on Computer Architecture (ISCA) 14-26 (IEEE, 2016). doi:10.1109/ISCA.2016.12. · DOI · Paper page
  8. [34]34. Pavan, P., Bez, R., Olivo, P. & Zanoni, E. Flash memory cells-an overview. Proc. IEEE 85 , 1248-1271 (1997).
  9. [38]38. Ramakrishnan, S., Hasler, P. E. & Gordon, C. Floating Gate Synapses With Spike-TimeDependent Plasticity. IEEE Trans. Biomed. Circuits Syst. 5 , 244-252 (2011).
  10. [43]43. Jang, J.-W., Park, S., Burr, G. W., Hwang, H. & Jeong, Y.-H. Optimization of Conductance Change in Pr1-x Cax MnO3 -Based Synaptic Devices for Neuromorphic Systems. IEEE Electron Device Lett. 36 , 457-459 (2015).
  11. [45]45. Milo, V. et al. Accurate Program/Verify Schemes of Resistive Switching Memory (RRAM) for In-Memory Neural Network Circuits. IEEE Trans. Electron Devices 68 , 3832-3837 (2021).
  12. [50]50. Lecun, Y., Bottou, L., Bengio, Y. & Haffner, P. Gradient-based learning applied to document recognition. Proc. IEEE 86 , 2278-2324 (1998).
  13. [52]52. Nandakumar, S. R. et al. Mixed-precision architecture based on computational memory for training deep neural networks. in International Symposium on Circuits and Systems (ISCAS) (2018).
  14. [54]54. Ma, Y. & Kan, E. Non-logic Devices in Logic Processes . Non-Logic Devices in Logic Processes (Springer International Publishing, 2017). doi:10.1007/978-3-319-48339-9. · DOI
  15. [55]55. Simon Tam, Ping-Keung Ko & Chenming Hu. Lucky-electron model of channel hot-electron injection in MOSFET'S. IEEE Trans. Electron Devices 31 , 1116-1125 (1984).
  16. [56]56. Yoshikawa, K. et al. Lucky-hole injection induced by band-to-band tunneling leakage in stacked gate transistors. in Technical Digest - International Electron Devices Meeting vol. 53 577-580 (1990).
  17. [57]57. Ielmini, D., Ghetti, A., Spinelli, A. S. & Visconti, A. A study of hot-hole injection during programming drain disturb in flash memories. IEEE Trans. Electron Devices 53 , 668-676 (2006).

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Authors
Wang, W., Danial, L., Li, Y., Herbelin, E., Pikhay, E., Roizin, Y., Hoffer, B., Wang, Z., & Kvatinsky, S.
Affiliations
  • Technion – Israel Institute of Technology (IL)
  • Tower Semiconductor (Israel) (IL)
  • University of Hong Kong (HK)
Corresponding author
  • Wang, Wei
  • Kvatinsky, Shahar
Venue
Nature Electronics
Published
2022-12-19
Volume
5
Issue
12
Pages
870-880
ISSN
2520-1131 (ISSN-L)
OpenAlex
W4313430026
Cited by
66
References
13
Citations by year
2026: 15 · 2025: 16 · 2024: 19 · 2023: 16
FWCI
3.49
Type
journal article
Language
en
Open access
Locations
  • Nature Electronics (publishedVersion)
  • arXiv (Cornell University) (submittedVersion)
  • arXiv (Cornell University)
Funders
European Commission (964877, 757259)
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
  • Physical Sciences › Computer Science › Artificial Intelligence › Neural Networks and Applications
Keywords
memristors, floating-gate devices, neuromorphic computing, in situ training, CMOS fabrication, device-to-device variation, contrastive divergence, handwritten digit recognition

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