Cited by 24Advanced Memory and Neural ComputingCognitive Computing and NetworksNeural Networks and Applications

Thermodynamic-RAM technology stack

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Nugent, M. Alexander, Molter, Timothy W.·2018·International Journal of Parallel, Emergent and Distributed Systems

Abstract

We introduce a technology stack or specification describing the multiple levels of abstraction and specialisation needed to implement a neuromorphic processor (NPU) based on the previously-described concept of AHaH Computing and integrate it into today’s digital computing systems. The general purpose NPU implementation described here is called Thermodynamic-RAM (kT-RAM) and is just one of many possible architectures, each with varying advantages and trade offs. Bringing us closer to brain-like neural computation, kT-RAM will provide a general-purpose adaptive hardware resource to existing computing platforms enabling fast and low-power machine learning capabilities that are currently hampered by the separation of memory and processing, a.k.a the von Neumann bottleneck. Because understanding such a processor based on non-traditional principles can be difficult, by presenting the various levels of the stack from the bottom up, layer by layer, explaining kT-RAM becomes a much easier task. The levels of the Thermodynamic-RAM technology stack include the memristor, synapse, AHaH node, kT-RAM, instruction set, sparse spike encoding, kT-RAM emulator, and SENSE server.

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Crossref · 10.1080/17445760.2017.1314472

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Authors
Nugent, M. A., & Molter, T. W.
Affiliations
Knowm Inc. , Santa Fe, NM, USA.
Corresponding author
Molter, Timothy W.
Venue
International Journal of Parallel, Emergent and Distributed Systems
Published
2017-04-18
Volume
33
Issue
4
Pages
430-444
ISSN
  • 1026-7689 (ISSN-L)
  • 1744-5760
  • 1744-5779
OpenAlex
W280546096
Cited by
23
References
29
Citations by year
2023: 2 · 2022: 6 · 2021: 1 · 2020: 5 · 2019: 4 · 2018: 3 · 2016: 2
FWCI
1.36
Type
journal article
Language
en
Open access
Locations
  • International Journal of Parallel Emergent and Distributed Systems (publishedVersion)
  • arXiv (Cornell University) (submittedVersion)
  • arXiv (Cornell University)
Funders
Air Force Research Labs (AF10-BT31,AF121-049)
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
  • Physical Sciences › Computer Science › Artificial Intelligence › Cognitive Computing and Networks
  • Physical Sciences › Computer Science › Artificial Intelligence › Neural Networks and Applications
Keywords
neuromorphic processors, technology stack, memristors, synapses, von Neumann bottleneck, instruction set architecture, low-power machine learning, neuromorphic computing

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