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A stochastic wire-length distribution for gigascale integration (GSI). II. Applications to clock frequency, power dissipation, and chip size estimation
Abstract
For pt.I see ibid., vol.45, no.3, pp.580-9 (Mar. 1998). Based on Rent's Rule, a well-established empirical relationship, a complete wire-length distribution for on-chip random logic networks is used to enhance a critical path model; to derive a preliminary dynamic power dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum interconnect density and minimum chip size.
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Citations
Cited by
Rationale and challenges for optical interconnects to electronic chips
Miller, D. A. B. (2000) · Proceedings of the IEEE · doi:10.1109/5.867687 · Cited by 1,189
A stochastic wire-length distribution for gigascale integration (GSI). I. Derivation and validation
Davis, J. A., De, V. K., & Meindl, J. D. (1998) · IEEE Transactions on Electron Devices · doi:10.1109/16.661219 · Cited by 329
Self-citationLanzerotti, M. Y., Fiorenza, G., & Rand, R. A. (2005) · IBM Journal of Research and Development · doi:10.1147/rd.494.0777 · Cited by 47
Metadata
- Authors
- Davis, J. A., De, V. K., & Meindl, J. D.
- Venue
- IEEE Transactions on Electron Devices
- Published
- 1998-03
- Volume
- 45
- Issue
- 3
- Pages
- 590-597
- ISSN
- 0018-9383 (ISSN-L)
- OpenAlex
- W2146306637
- Cited by
- 240
- References
- 0
- FWCI
- 23.34
- Type
- journal article
- Language
- en
- Open access
- closed
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- Davis, J. A., De, V. K., & Meindl, J. D. (1998). A stochastic wire-length distribution for gigascale integration (GSI). II. Applications to clock frequency, power dissipation, and chip size estimation. IEEE Transactions on Electron Devices. https://doi.org/10.1109/16.661220
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Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.