Rationale and challenges for optical interconnects to electronic chips
Abstract
The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedence matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chop global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects.
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Limitations of microelectronic technologies can be avoided by using photons as a signal carrier.
“These limitations can be avoided by using photons as a signal carrier [32].”
From The Current State of Optical Sensors in Medical Wearables (2022) · cites this paper as [32]
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“These limitations can be avoided by using photons as a signal carrier [32].”
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- Authors
- Miller, D. A. B.
- Affiliations
- Stanford University (US)
- Corresponding author
- Miller, D.A.B.
- ORCID
- Miller, D.A.B.
- Venue
- Proceedings of the IEEE
- Published
- 2000-06
- Volume
- 88
- Issue
- 6
- Pages
- 728-749
- ISSN
- 0018-9219 (ISSN-L)
- 1558-2256
- OpenAlex
- W2111655361
- Cited by
- 1,189
- References
- 136
- Citations by year
- 2026: 10 · 2025: 25 · 2024: 30 · 2023: 35 · 2022: 32 · 2021: 21 · 2020: 26 · 2019: 32 · 2018: 45 · 2017: 47 · 2016: 44 · 2015: 49 · 2014: 53 · 2013: 62 · 2012: 67
- FWCI
- 34.16
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- Proceedings of the IEEE (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Semiconductor Lasers and Optical Devices
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Photonic and Optical Devices
- Physical Sciences › Computer Science › Computer Networks and Communications › Interconnection Networks and Systems
- Keywords
- optical interconnects, optoelectronic integration, clock distribution, system synchronization, crosstalk, voltage isolation, impedance matching, power dissipation, interconnect scaling, line inductance, skin effect
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
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