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FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Abstract
MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed. By using boron-doped Si/sub 0.4/Ge/sub 0.6/ as a gate material, the desired threshold voltage was achieved for the ultrathin body device. The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily using the conventional planar MOSFET process technologies.
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Citations
Cited by
Frontiers of silicon-on-insulator
Celler, G. K., & Cristoloveanu, S. (2003) · Journal of Applied Physics · doi:10.1063/1.1558223 · Cited by 699
Limits on fundamental limits to computation
Markov, I. L. (2014) · Nature · doi:10.1038/nature13570 · Cited by 494
Liu, Y., Matsukawa, T., Endo, K., Masahara, M., O'uchi, S.-I., Ishii, K., Yamauchi, H., Tsukada, J., Ishikawa, Y., & Suzuki, E. (2007) · IEEE Electron Device Letters · doi:10.1109/led.2007.896898 · Cited by 54
Investigation of Sidewall High-k Interfacial Layer Effect in Gate-All-Around Structure
Ryu, D., Kim, M., Yu, J., Kim, S., Lee, J.-H., & Park, B.-G. (2020) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2020.2975255 · Cited by 40
A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects
Ramezani, Z., & Orouji, A. A. (2017) · International Journal of Electronics · doi:10.1080/00207217.2017.1357206 · Cited by 31
Metadata
- Authors
- Hu, C., Bokor, J., King, T.-J., Anderson, E., Kuo, C., Asano, K., Takeuchi, H., Kedzierski, J., Lee, W.-C., & Hisamoto, D.
- Venue
- IEEE Transactions on Electron Devices
- Published
- 2000
- Volume
- 47
- Issue
- 12
- Pages
- 2320-2325
- ISSN
- 0018-9383 (ISSN-L)
- OpenAlex
- W2135818056
- Cited by
- 1,660
- References
- 0
- FWCI
- 20.36
- Type
- journal article
- Language
- en
- Open access
- closed
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- Hu, C., Bokor, J., King, T.-J., Anderson, E., Kuo, C., Asano, K., Takeuchi, H., Kedzierski, J., Lee, W.-C., & Hisamoto, D. (2000). FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Transactions on Electron Devices. https://doi.org/10.1109/16.887014
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Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.
