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Charge-trap memory device fabricated by oxidation of Si/sub 1-x/Ge/sub x/
Abstract
In this work, we describe a novel technique of fabricating germanium nanocrystal quasi-nonvolatile memory device. The device consists of a metal-oxide-semiconductor field-effect transistor (MOSFET) with Ge charge-traps embedded within the gate dielectric. The trap formation method provides for precise control of the thicknesses of the top (control) and bottom (tunneling) oxide layers which sandwich the charge-traps, via thermal oxidation. This memory device exhibits write/erase speed/voltage and retention time superior to previously reported nano-crystal or charge-trap memory devices. A detailed description of the novel process for fabricating the Ge charge-trap MOS memory is given, along with the resultant memory-cell performance characteristics.
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Cited by
Memory effects in complex materials and nanoscale systems
Pershin, Y. V., & Di Ventra, M. (2011) · Advances In Physics · doi:10.1080/00018732.2010.544961 · Cited by 823
Metal nanocrystal memories. I. Device design and fabrication
Liu, Z., Lee, C., Narayanan, V., Pei, G., & Kan, E. C. (2002) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2002.802617 · Cited by 482
Metadata
- Authors
- King, Y.-C., King, T.-J., & Hu, C.
- Venue
- IEEE Transactions on Electron Devices
- Published
- 2001-04
- Volume
- 48
- Issue
- 4
- Pages
- 696-700
- ISSN
- 0018-9383 (ISSN-L)
- OpenAlex
- W2002711800
- Cited by
- 229
- References
- 0
- FWCI
- 20.91
- Type
- journal article
- Language
- en
- Open access
- closed
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- King, Y.-C., King, T.-J., & Hu, C. (2001). Charge-trap memory device fabricated by oxidation of Si/sub 1-x/Ge/sub x/. IEEE Transactions on Electron Devices. https://doi.org/10.1109/16.915694
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