The DOI matches its Crossref record; 8 of the 8 references it cites were found in a registry or an index.
Metal nanocrystal memories. I. Device design and fabrication
Abstract
This paper describes the design principles and fabrication process of metal nanocrystal memories. The advantages of metal nanocrystals over their semiconductor counterparts include higher density of states, stronger coupling with the channel, better size scalability, and the design freedom of engineering the work functions to optimize device characteristics. One-dimensional (1-D) analyses are provided to illustrate the concept of work function engineering, both in direct-tunneling and F-N-tunneling regimes. A self-assembled nanocrystal formation process by rapid thermal annealing of ultrathin metal film deposited on top of gate oxide is developed and integrated with NMOSFET to fabricate such devices.
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Citations
Cites
Single-electron devices and their applications
Likharev, K. K. (1999) · Proceedings of the IEEE · doi:10.1109/5.752518 · Cited by 1,453
Fast and long retention-time nano-crystal memory
Hanafi, H. I., Tiwari, S., & Khan, I. (1996) · IEEE Transactions on Electron Devices · doi:10.1109/16.535349 · Cited by 479
Charge-trap memory device fabricated by oxidation of Si/sub 1-x/Ge/sub x/
King, Y.-C., King, T.-J., & Hu, C. (2001) · IEEE Transactions on Electron Devices · doi:10.1109/16.915694 · Cited by 229
Room temperature operation of a quantum-dot flash memory
Welser, J. J., Tiwari, S., Rishton, S., Lee, K. Y., & Lee, Y. (1997) · IEEE Electron Device Letters · doi:10.1109/55.585357 · Cited by 195
Metal nanocrystal memories-part II: electrical characteristics
Liu, Z., Lee, C., Narayanan, V., Pei, G., & Kan, E. C. (2002) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2002.802618 · Cited by 188
Self-citationHigh-endurance ultra-thin tunnel oxide in MONOS device structure for dynamic memory application
Wann, H. C., & Hu, C. C. (1995) · IEEE Electron Device Letters · doi:10.1109/55.468277 · Cited by 49
Process and device characteristics of self-assembled metal nano-crystal EEPROM
Liu, Z., Kim, M., Narayanan, V., & Kan, E. C.-C. (2000) · Superlattices and Microstructures · doi:10.1006/spmi.2000.0939 · Cited by 21
Self-citationDirected self-assembly process for nano-electronic devices and interconnect
Kan, E. C.-C., & Liu, Z. (2000) · Superlattices and Microstructures · doi:10.1006/spmi.2000.0851 · Cited by 13
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Cited by
Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties
Lee, J.-S., Cho, J., Lee, C., Kim, I., Park, J., Kim, Y.-M., Shin, H., Lee, J., & Caruso, F. (2007) · Nature Nanotechnology · doi:10.1038/nnano.2007.380 · Cited by 265
Self-citationA wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement
Kim, J., Son, D., Lee, M., Song, C., Song, J.-K., Koo, J. H., Lee, D. J., Shim, H. J., Kim, J. H., Lee, M., et al. (2016) · Science Advances · doi:10.1126/sciadv.1501101 · Cited by 164
Metadata
- Authors
- Liu, Z., Lee, C., Narayanan, V., Pei, G., & Kan, E. C.
- Venue
- IEEE Transactions on Electron Devices
- Published
- 2002-09
- Volume
- 49
- Issue
- 9
- Pages
- 1606-1613
- ISSN
- 0018-9383 (ISSN-L)
- OpenAlex
- W2170323059
- Cited by
- 482
- References
- 8
- FWCI
- 17.53
- Type
- journal article
- Language
- en
- Open access
- closed
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- Liu, Z., Lee, C., Narayanan, V., Pei, G., & Kan, E. C. (2002). Metal nanocrystal memories. I. Device design and fabrication. IEEE Transactions on Electron Devices. https://doi.org/10.1109/ted.2002.802617
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Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
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