Cited by 11Metaheuristic Optimization Algorithms ResearchParallel Computing and Optimization TechniquesEmbedded Systems Design Techniques

A General Framework for Accelerating Swarm Intelligence Algorithms on FPGAs, GPUs and Multi-Core CPUs

Open access
Li, Dalin, Huang, Lan, Wang, Kangping, Pang, Wei, Zhou, You, Zhang, Rui·2018·IEEE Access

Abstract

Swarm intelligence algorithms (SIAs) have demonstrated excellent performance when solving optimization problems including many real-world problems. However, because of their expensive computational cost for some complex problems, SIAs need to be accelerated effectively for better performance. This paper presents a high-performance general framework to accelerate SIAs (FASI). Different from the previous work which accelerates SIAs through enhancing the parallelization only, FASI considers both the memory architectures of hardware platforms and the dataflow of SIAs, and it reschedules the framework of SIAs as a converged dataflow to improve the memory access efficiency. FASI achieves higher acceleration ability by matching the algorithm framework to the hardware architectures. We also design deep optimized structures of the parallelization and convergence of FASI based on the characteristics of specific hardware platforms. We take the quantum behaved particle swarm optimization algorithm as a case to evaluate FASI. The results show that FASI improves the throughput of SIAs and provides better performance through optimizing the hardware implementations. In our experiments, FASI achieves a maximum of 290.7 Mb/s throughput which is higher than several existing systems, and FASI on FPGAs achieves a better speedup than that on GPUs and multi-core CPUs. FASI is up to 123 times and not less than 1.45 times faster in terms of optimization time on Xilinx Kintex Ultrascale xcku040 when compares to Intel Core i7-6700 CPU/NVIDIA GTX1080 GPU. Finally, we compare the differences of deploying FASI on hardware platforms and provide some guidelines for promoting the acceleration performance according to the hardware architectures.

Integrity signals

Registry

Crossref · 10.1109/access.2018.2882455

Cites

42 of 42 references verified0 citation errors · 0 not checkable

Statistics

Recomputing p-values needs the paper’s full text.

Claims the paper makes

We couldn’t retrieve this paper’s full text, so its claims and self-check weren’t run. The registry and citation checks still apply.

Claims other papers make about this one

Each is checked against this paper’s own text: does it say what the citing paper says it does?

  • Full pipelined FASI in FPGA allows the map dimension, map particle, combiner and reducer global to be pipelined together for higher throughput.

    “In addition, full pipelined FASI in FPGA, where the reductions and combinations are pipelined together with the threads, as shown in Figure 13, allows the map dimension, map particle, combiner and reducer global to be pipelined together for higher throughput.”

Cites

Flagged first, then by citations

Cited by

Sorted by citations

Authors
Li, D., Huang, L., Wang, K., Pang, W., Zhou, Y., & Zhang, R.
Affiliations
  • Jilin University (CN)
  • University of Aberdeen (GB)
Venue
IEEE Access
Published
2018
Volume
6
Pages
72327-72344
ISSN
2169-3536 (ISSN-L)
OpenAlex
W2901663594
Cited by
11
References
42
Citations by year
2025: 2 · 2023: 1 · 2022: 1 · 2021: 4 · 2020: 2 · 2019: 1
FWCI
0.98
Type
journal article
Language
en
Open access
Locations
  • IEEE Access (publishedVersion)
  • Aberdeen University Research Archive (Aberdeen University) (submittedVersion)
  • DOAJ (DOAJ: Directory of Open Access Journals) (submittedVersion, cc-by-sa)
Funders
  • National Natural Science Foundation of China (61472159, 61572227, 61772227)
  • Development Project of Jilin Province of China (20160204022GX, 20170101006JC, 20170203002GX, 2017C030-1, 2017C033)
  • Premier-Discipline Enhancement Scheme through Zhuhai Government
  • Premier Key-Discipline Enhancement Scheme through the Guangdong Government Funds
  • Jilin Provincial Key Laboratory of Big Data Intelligent Computing (20180622002JC)
Topics
  • Physical Sciences › Computer Science › Artificial Intelligence › Metaheuristic Optimization Algorithms Research
  • Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
  • Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
Keywords
swarm intelligence algorithms, hardware acceleration, FPGA, graphics processing units, multi-core processors, quantum-behaved particle swarm optimization, memory access efficiency, parallelization, throughput

About these checks

Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.

Statistics and arithmetic are recomputed, not judged.

Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.

What counts as a claim ›How we measure confidence ›How we check this ›

Are you an author, or do you see a problem with this page? Request a review