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Cited by 23ECG Monitoring and AnalysisAnalog and Mixed-Signal Circuit DesignLow-power high-performance VLSI design

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A Neural Network-Based ECG Classification Processor With Exploitation of Heartbeat Similarity

Open access
Wu, Jiaquan, Li, Feiteng, Chen, Zhijian, Pu, Yu, Zhan, Mengyuan·2019·IEEE Access
DOI 10.1109/access.2019.2956179
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Abstract

This paper presents a neural network based processor with improved computation efficiency, which aims at multiclass heartbeat recognition in wearable devices. A lightweight classification algorithm that integrates both bi-directional long short-term memory (BLSTM) and convolutional neural networks (CNN) is proposed to deliver high accuracy with minimal network scale. To reduce energy consumption of the classification algorithm, the similarity between consecutive heartbeats is exploited to achieve a high degree of computation reuse in hardware architecture. In addition, neural network compression techniques are adopted in the procedure of inference to save hardware resources. Synthesized in the SMIC 40LL CMOS process, the prototype design has a total area of 1.40 mm2with 186.2 kB of static random-access memory (SRAM) capacity. Based on the simulation, this processor achieves an average energy efficiency of 3.52 GOPS/mW under 1.1 V supply at 100 MHz frequency. Compared with the design without computation reuse, the proposed processor provides a speedup by 2.58x and an energy dissipation reduction by 61.27% per classification. This work is a valuable exploration of neural network based design for long-term arrhythmia monitoring in daily life.

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Figures

FIGURE 1 One typical heartbeat in ECG signal with significant details, including the P, Q, R, S, and T waves.
FIGURE 1 One typical heartbeat in ECG signal with significant details, including the P, Q, R, S, and T waves.CC-BY · From the PDF
FIGURE 2 The architecture of the proposed ECG classification algorithm. The ECG waveforms of two signal channels after baseline wander removing are first segmented into single heartbeats and then resampled as the inputs of BLSTM and CNN. The locations of R waves are adopted as reference to extract heartbeats with adaptive lengths according to the average RR interval D .
FIGURE 2 The architecture of the proposed ECG classification algorithm. The ECG waveforms of two signal channels after baseline wander removing are first segmented into single heartbeats and then resampled as the inputs of BLSTM and CNN. The locations of R waves are adopted as reference to extract heartbeats with adaptive lengths according to the average RR interval D .CC-BY · From the PDF
FIGURE 3 The system overview of the proposed processor. The weights of BLSTM, CNN and MLP layers are stored in SRAMs and read out to corresponding weight buffers independently. The PE array accomplishes the MAC operations and non-linear operations with the reuse of the MAC Matrix. The intermediate results are stored in the Buffer SRAM. The top-level logic is responsible for the control of the whole system.
FIGURE 3 The system overview of the proposed processor. The weights of BLSTM, CNN and MLP layers are stored in SRAMs and read out to corresponding weight buffers independently. The PE array accomplishes the MAC operations and non-linear operations with the reuse of the MAC Matrix. The intermediate results are stored in the Buffer SRAM. The top-level logic is responsible for the control of the whole system.CC-BY · From the PDF
Image 4
CC-BY · From the PDF
FIGURE 5 The computation reuse based architecture for the BLSTM. The 4-bit quantized weight indexes are read out from the SRAMs and mapped to 8-bit fixed-point format through the LUT. The PE array achieves the multiplication between the remainders of adjacent layers and corresponding weights. The intermediate results are processed by the buffer register files and Ping-Pong SRAM. Zero-detect logic finds the zero related operations to be skipped during the computation. The intermediate MAC results of each time step are stored in the cache SRAM array to achieve the computation reuse design for input overlap.
FIGURE 5 The computation reuse based architecture for the BLSTM. The 4-bit quantized weight indexes are read out from the SRAMs and mapped to 8-bit fixed-point format through the LUT. The PE array achieves the multiplication between the remainders of adjacent layers and corresponding weights. The intermediate results are processed by the buffer register files and Ping-Pong SRAM. Zero-detect logic finds the zero related operations to be skipped during the computation. The intermediate MAC results of each time step are stored in the cache SRAM array to achieve the computation reuse design for input overlap.CC-BY · From the PDF
FIGURE 6 The input overlap is utilized to achieve computation reuse for the BLSTM topology. The intermediate results of the last N-1 time steps in the current inference are the same as those of the first N-1 time steps in the next inference. Only the last one time step needs to calculate the new matrix-vector results except for the first inference.
FIGURE 6 The input overlap is utilized to achieve computation reuse for the BLSTM topology. The intermediate results of the last N-1 time steps in the current inference are the same as those of the first N-1 time steps in the next inference. Only the last one time step needs to calculate the new matrix-vector results except for the first inference.CC-BY · From the PDF
FIGURE 7 Layout of the proposed ECG processor in the SMIC 40LL process.
FIGURE 7 Layout of the proposed ECG processor in the SMIC 40LL process.CC-BY · From the PDF
Image 8
CC-BY · From the PDF
Image 9
CC-BY · From the PDF
Image 10
CC-BY · From the PDF
Image 11
CC-BY · From the PDF
Image 12
CC-BY · From the PDF

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References 23 · Cited by 23

Research works printed but not linked: 3

  1. 1987, Recommended practice for testing and reporting performance results of ventricular arrhythmia detection algorithms, Journal of Assoc Advancement of Medical Instr, 69
  2. saadatnejad, 0, LSTM-based ECG classification for continuous monitoring on personal wearable devices, IEEE J Biomed Health Inform
  3. mark, 1988, MIT-BIH arrhythmia database directory

Metadata

Authors
Wu, J., Li, F., Chen, Z., Pu, Y., & Zhan, M.
Affiliations
  • Zhejiang University (CN)
  • Affiliated Hospital of Qingdao University (CN)
ORCID
Venue
IEEE Access
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Published
2019
Volume
7
Pages
172774-172782
ISSN
2169-3536 (ISSN-L)
DOI
10.1109/access.2019.2956179
OpenAlex
W2990225235
Cited by
23
References
23
Citations by year
2026: 2 · 2025: 4 · 2024: 6 · 2023: 1 · 2022: 5 · 2021: 5
FWCI
1.83
Type
journal article
Language
en
Open access
Licence
Locations
  • IEEE Access (publishedVersion, cc-by)
  • DOAJ (DOAJ: Directory of Open Access Journals) (submittedVersion, cc-by-sa)
Funders
National Natural Science Foundation of China (61801425)
Topics
  • Health Sciences › Medicine › Cardiology and Cardiovascular Medicine › ECG Monitoring and Analysis
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Analog and Mixed-Signal Circuit Design
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
Keywords
ECG classification, wearable devices, multi-class classification, bidirectional LSTM, convolutional neural networks, computation reuse, energy efficiency, neural network compression, hardware accelerators, arrhythmia monitoring, CMOS VLSI design

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CoChat. (2026). Citation check: A Neural Network-Based ECG Classification Processor With Exploitation of Heartbeat Similarity. https://app.cochat.ai/papers/10.1109/access.2019.2956179
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Wu, J., Li, F., Chen, Z., Pu, Y., & Zhan, M. (2019). A Neural Network-Based ECG Classification Processor With Exploitation of Heartbeat Similarity. IEEE Access. https://doi.org/10.1109/access.2019.2956179

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