Optimization of advanced encryption standard on graphics processing units
Open accessAbstract
Graphics processing units (GPUs) are specially designed for parallel applications and perform parallel operations much faster than central processing units (CPUs). In this work, we focus on the performance of the Advanced Encryption Standard (AES) on GPUs. We present optimizations which remove bank conflicts in shared memory accesses and provide 878.6 Gbps throughput for AES-128 encryption on an RTX 2070 Super, which is equivalent to 4.1 Gbps per Watt. Our optimizations provide more than 2.56x speed-up against the best GPU results in the literature. Our optimized AES implementations on GPUs even outperform any CPU using the hardware level AES New Instructions (AES-NI) and legacy FPGA-based cluster architectures like COPACOBANA and RIVYERA. Even on a low-end GPU like MX 250, we obtained 60.0 Gbps throughput for AES-256 which is generally faster than the read/write speeds of solid disks. Thus, transition from AES-128 to AES-256 when using GPUs would provide military grade security with no visible performance loss. With these breakthrough performances, GPUs can be used as a cryptographic co-processor for file or full disk encryption to remove performance loss coming from CPU encryption. With a single GPU as a co-processor, busy SSL servers can be free from the burden of encryption and use their whole CPU power for other operations. Moreover, these optimizations can help GPUs to practically verify theoretically obtained cryptanalysis results or their reduced versions in reasonabl…
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Prior optimized AES-CTR implementations have achieved approximately 878 Gbps on consumer hardware (Tezcan, 2021).
“Within the GPU tier, prior optimized AES-CTR implementations have achieved approximately 878 Gbps on consumer hardware (Tezcan, 2021), providing additional context for the GPU cryptographic performance envelope demonstrated here.”
From A high-throughput AES-GCM implementation on GPUs for secure, policy-based access to massive astronomical catalogs (2026) · cites this paper as Tezcan, 2021
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FPGA-friendly compact and efficient AES-like 8 × 8 S-box
Malal, A., & Tezcan, C. (2024) · Microprocessors and Microsystems · doi:10.1016/j.micpro.2024.105007 · Cited by 7 · see citing works
Self-citationMalal, A., & Tezcan, C. (2026) · Journal of Cryptographic Engineering · doi:10.1007/s13389-025-00388-2 · Cited by 3 · see citing works
“Thisisbecausesomeofthethroughputresults of [6] were provided by considering giga, mega, and kilo terms as a multiple of 1024 as commonly used in storage.”
InfluentialSelf-citationLemes-Perera, S., R. Alarcon, M., Caballero-Gil, P., & Serra-Ricart, M. (2026) · Astronomy and Computing · doi:10.1016/j.ascom.2026.101153 · Cited by 1 · see citing works
- Authors
- Tezcan, C.
- Affiliations
- Middle East Technical University (TR)
- Corresponding author
- Tezcan, Cihangir
- ORCID
- Tezcan, Cihangir
- Venue
- IEEE Access
- Published
- 2021
- Volume
- 9
- Pages
- 67315-67326
- ISSN
- 2169-3536 (ISSN-L)
- OpenAlex
- W3160691049
- Cited by
- 45
- References
- 0
- Citations by year
- 2026: 12 · 2025: 8 · 2024: 9 · 2023: 5 · 2022: 10 · 2021: 1
- FWCI
- 2.21
- Type
- journal article
- Language
- en
- Open access
- gold
- doi.org
- Licence
- Locations
- IEEE Access (publishedVersion, cc-by-nc-nd)
- DOAJ (DOAJ: Directory of Open Access Journals) (submittedVersion, cc-by-sa)
- OpenMETU (Middle East Technical University) (submittedVersion, cc-by-nc-nd)
- Topics
- Physical Sciences › Computer Science › Artificial Intelligence › Cryptographic Implementations and Security
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Physical Sciences › Computer Science › Information Systems › Cryptography and Residue Arithmetic
- Keywords
- Advanced Encryption Standard, GPU acceleration, AES-128, AES-256, cryptographic coprocessor, parallel encryption, encryption throughput, energy efficiency, full disk encryption
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