FPGA-friendly compact and efficient AES-like 8 × 8 S-box

Differential cryptanalysis of DES-like cryptosystems

Biham, E., & Shamir, A. (1991) · Journal of Cryptology · doi:10.1007/bf00630563 · Cited by 2,914 · see citing works

The design of Rijndael AES - the advanced encryption standard

Daemen, J., & Rijmen, V. (2002) · Cited by 2,876 · see citing works

Linear Cryptanalysis Method for DES Cipher

Matsui, M. (1994) · Lecture Notes in Computer Science · doi:10.1007/3-540-48285-7_33 · Cited by 2,748 · see citing works

A Compact Rijndael Hardware Architecture with S-Box Optimization

Satoh, A., Morioka, S., Takano, K., & Munetoh, S. (2001) · Lecture notes in computer science · doi:10.1007/3-540-45682-1_15 · Cited by 685 · see citing works

The Boomerang Attack

Wagner, D. A. (1999) · Lecture notes in computer science · doi:10.1007/3-540-48519-8_12 · Cited by 607 · see citing works

A Very Compact S-Box for AES

Canright, D. (2005) · Lecture Notes in Computer Science · doi:10.1007/11545262_32 · Cited by 530 · see citing works

Boomerang Connectivity Table: A New Cryptanalysis Tool

Cid, C., Huang, T., Peyrin, T., Sasaki, Y., & Song, L. (2018) · Lecture notes in computer science · doi:10.1007/978-3-319-78375-8_22 · Cited by 196 · see citing works

An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm

Saggese, G. P., Mazzeo, A., Mazzocca, N., & Strollo, A. G. M. (2003) · Lecture notes in computer science · doi:10.1007/978-3-540-45234-8_29 · Cited by 122 · see citing works

On the Boomerang Uniformity of Cryptographic Sboxes

Boura, C., & Canteaut, A. (2018) · IACR Transactions on Symmetric Cryptology · doi:10.46586/tosc.v2018.i3.290-310 · Cited by 106 · see citing works

FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network

Wang, Y., & Ha, Y. (2013) · IEEE Transactions on Circuits & Systems II Express Briefs · doi:10.1109/tcsii.2012.2234891 · Cited by 99 · see citing works

2012 10th International Conference on Frontiers of Information Technology

(2012) · doi:10.1109/fit21088.2012 · Cited by 61 · see citing works

FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications

Murugan, C. A., Karthigaikumar, P., & Priya, S. S. S. (2020) · Automatika · doi:10.1080/00051144.2020.1816388 · Cited by 56 · see citing works

Optimization of advanced encryption standard on graphics processing units

Tezcan, C. (2021) · IEEE Access · doi:10.1109/access.2021.3077551 · Cited by 45 · see citing works

2015 4th International Conference on Electrical Engineering (ICEE)

(2015) · doi:10.1109/icee36789.2015 · Cited by 44 · see citing works

Implementation of Bitsliced AES Encryption on CUDA-Enabled GPU

Nishikawa, N., Amano, H., & Iwai, K. (2017) · Lecture Notes in Computer Science · doi:10.1007/978-3-319-64701-2_20 · Cited by 42 · see citing works

Secure communication through reliable S-box design: A proposed approach using coset graphs and matrix operations

Razaq, A., Alhamzi, G., Abbas, S. M., Ahmad, M., & Razzaque, A. (2023) · Heliyon · doi:10.1016/j.heliyon.2023.e15902 · Cited by 40 · see citing works

2021 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia)

(2021) · doi:10.1109/icce-asia53811.2021 · Cited by 37 · see citing works

Advances in Cryptology - CRYPTO '90, 10th Annual International Cryptology Conference, Santa Barbara, California, USA, August 11-15, 1990, Proceedings

Menezes, A., & Vanstone, S. A. (1991) · Cited by 33 · see citing works

Counting Irreducible Polynomials over Finite Fields Using the Inclusion-Exclusion Principle

Chebolu, S. K., & Mináč, J. (2011) · Mathematics Magazine · doi:10.4169/math.mag.84.5.369 · Cited by 31 · see citing works

A high performance ST-Box based unified AES encryption/decryption architecture on FPGA

Kundi, D. S., Aziz, A., & Ikram, N. (2015) · Microprocessors and Microsystems · doi:10.1016/j.micpro.2015.11.015 · Cited by 31 · see citing works

High performance CUDA AES implementation: A quantitative performance analysis approach

Abdelrahman, A. A., Fouad, M. M., Dahshan, H., & Mousa, A. M. (2017) · 2017 Computing Conference · doi:10.1109/sai.2017.8252225 · Cited by 31 · see citing works

FPGA implementation of highly scalable AES algorithm using modified mix column with gate replacement technique for security application in TCP/IP

Madhavapandian, S., & Maruthupandi, P. (2019) · Microprocessors and Microsystems · doi:10.1016/j.micpro.2019.102972 · Cited by 30 · see citing works

Advances in cryptology, EUROCRYPT '93 : Workshop on the Theory and Application of Cryptographic Techniques, Lofthus, Norway, May 23-27, 1993 : proceedings

Helleseth, T. (1994) · Medical Entomology and Zoology · Cited by 29 · see citing works

An Efficient High Throughput FPGA Implementation of AES for Multi-gigabit Protocols

Hussain, U., & Jamal, H. (2012) · International Conference on Frontiers of Information Technology (FIT) · doi:10.1109/fit.2012.45 · Cited by 27 · see citing works

Highly Efficient Implementation of Block Ciphers on Graphic Processing Units for Massively Large Data

An, S., & Seo, S. C. (2020) · Applied Sciences · doi:10.3390/app10113711 · Cited by 26 · see citing works

Reliable advanced encryption standard hardware implementation: 32- bit and 64-bit data-paths

Sheikhpour, S., Mahani, A. K., & Bagheri, N. (2020) · Microprocessors and Microsystems · doi:10.1016/j.micpro.2020.103740 · Cited by 26 · see citing works

An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box

Priya, S. S. S., Karthigaikumar, P., Mangai, N. M. S., & Das, P. K. G. (2016) · Wireless Personal Communications · doi:10.1007/s11277-016-3385-7 · Cited by 25 · see citing works

Enhancing the security of AES through small scale confusion operations for data communication

Lavanya, R., & Karpagam, M. (2020) · Microprocessors and Microsystems · doi:10.1016/j.micpro.2020.103041 · Cited by 25 · see citing works

A Survey on Performance Analysis of Different Architectures of AES Algorithm on FPGA

Hasija, T., Kaur, A., Ramkumar, K. R., Sharma, S., Mittal, S. K., & Singh, B. (2023) · Lecture notes in electrical engineering · doi:10.1007/978-981-19-6383-4_4 · Cited by 25 · see citing works

Advances in cryptology--ASIACRYPT 2001 : 7th International Conference on the Theory and Application of Cryptology and Information Security, Gold Coast, Australia, December 9-13, 2001 : proceedings

Boyd, C. (2001) · Cited by 23 · see citing works

Revisiting AES SBox Composite Field Implementations for FPGAs

Pradeep, A., Mohanty, V., Subramaniam, A. M., & Rebeiro, C. (2019) · IEEE Embedded Systems Letters · doi:10.1109/les.2019.2899113 · Cited by 20 · see citing works

Key lengths revisited: GPU-based brute force cryptanalysis of DES, 3DES, and PRESENT

Tezcan, C. (2022) · Journal of Systems Architecture · doi:10.1016/j.sysarc.2022.102402 · Cited by 20 · see citing works

MEMORY EFFICIENT IMPLEMENTATION OF AES S-BOXES ON FPGA

Aziz, A., & Ikram, N. (2007) · Journal of Circuits Systems and Computers · doi:10.1142/s0218126607003873 · Cited by 19 · see citing works

An efficient S-box design scheme for image encryption based on the combination of a coset graph and a matrix transformer

Razzaque, A., Razaq, A., Farooq, S. M., Masmali, I. A. H., & Faraz, M. I. (2023) · Electronic Research Archive · doi:10.3934/era.2023137 · Cited by 18 · see citing works

A Survey on VLSI Implementation of AES Algorithm with Dynamic S-Box

Dhanalakshmi, K. S., & Padmavathi, R. A. (2021) · Journal of Applied Security Research · doi:10.1080/19361610.2020.1870403 · Cited by 15 · see citing works

Hardware Implementation of AES with S-Box Using Composite-Field for WLAN Systems

Huy, D. Q., Duc, N. M., Khai, L. D., & Lung, V. D. (2019) · RIVF International Conference on Computing and Communication Technologies (RIVF) · doi:10.1109/rivf.2019.8713711 · Cited by 14 · see citing works

Design feasibility study for a 500 Gbits/s advanced encryption standard cipher/decipher engine

Bouhraoua, A. (2010) · IET Computers & Digital Techniques · doi:10.1049/iet-cdt.2009.0023 · Cited by 9 · see citing works

Hardware security platform for multicast communications

Granado-Criado, J. M., Vega-Rodríguez, M. A., Sanchez-Perez, J. M., & Gomez-Pulido, J. A. (2013) · Journal of Systems Architecture · doi:10.1016/j.sysarc.2013.11.007 · Cited by 8 · see citing works

Advanced Encryption Standard - AES: 4th International Conference, AES 2004, Bonn, Germany, May 10-12, 2004, Revised Selected and Invited Papers

Dobbertin, H., Rijmen, V., & Sowa, A. (2005) · doi:10.1007/b137765 · Cited by 7 · see citing works

Fast software encryption : 6th International Workshop, FSE'99, Rome, Italy, March 24-26, 1999 : proceedings

Knudsen, L. R. (1999) · Springer eBooks · Cited by 6 · see citing works

Progress in cryptology-AFRICACRYPT 2008 : first international conference on cryptology in Africa, Casablanca, Morocco, June 11-14, 2008 : proceedings

Vaudenay, S. (2008) · doi:10.1007/978-3-540-68164-9 · Cited by 6 · see citing works

Cryptographic hardware and embedded systems - CHES 2005 : 7th International Workshop, Edinburgh, UK, August 29-September 1, 2005 : proceedings

Rao, J. R., & Sunar, B. (2005) · Digital Access to Libraries (Université catholique de Louvain (UCL), l'Université de Namur (UNamur) and the Université Saint-Louis (USL-B)) · doi:10.1007/11545262 · Cited by 5 · see citing works

Modern Electronics Devices and Communication Systems

Agrawal, R., Singh, C. K., Goyal, A., & Singh, D. K. (2023) · Lecture notes in electrical engineering · doi:10.1007/978-981-19-6383-4 · Cited by 5 · see citing works

Study on Optimizing Block Ciphers (AES, CHAM) on Graphic Processing Units

An, S. W., & Seo, S. C. (2020) · IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia) · doi:10.1109/icce-asia49877.2020.9276980 · Cited by 5 · see citing works

The Cryptanalysis of the AES - A Brief Survey

Knudsen, L. R. (2005) · Technical University of Denmark, DTU Orbit (Technical University of Denmark, DTU) · Cited by 1 · see citing works

Lightweight AES Design for IoT Applications: Optimizations in FPGA and ASIC With DFA Countermeasure Strategies

Ahmed, S., Ahmad, N. B., Shah, N. A., Abro, G. E. M., Wijayanto, A., Hirsi, A., & Altaf, A. R. (2025) · IEEE Access · doi:10.1109/access.2025.3533611 · Cited by 42 · see citing works

First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES

Malal, A., & Tezcan, C. (2026) · Journal of Cryptographic Engineering · doi:10.1007/s13389-025-00388-2 · Cited by 3 · see citing works

First-Order Threshold Implementation of AES Against Side-Channel Attacks on FPGA

Çalıkuş, A., Çalışkan, Ş., Örs, B., MALAL, A., Kaan, E. K. E. R., & Aksoy, B. (2025) · doi:10.1109/isctrkiye68593.2025.11224814 · Cited by 2 · see citing works

Modified Lightweight Advanced Encryption Standard for Lightweight Embedded Applications

Sama, A., Meyliana, M., Heryadi, Y., & Sahroni, ⁠. R. (2025) · International Journal of Safety and Security Engineering · doi:10.18280/ijsse.150415 · Cited by 1 · see citing works

Square Transposition Method with Adaptive Key Flexibility and Strong Diffusion Performance

Pakereng, M. A. I., Wowor, A. D., Beeh, Y. R., David, F., Christianto, E., Susanto, V. E., & Canavaro, C. (2025) · Matrik Jurnal Manajemen Teknik Informatika dan Rekayasa Komputer · doi:10.30812/matrik.v24i3.5004

FPGA-Based Cosimulation of S-Box Constitution from Fractional Order Liu System

Arseri̇m, M. A., & Türk, Ö. (2025) · DÜMF Mühendislik Dergisi · doi:10.24012/dumf.1822418

Design and Implementation of an AES Hardware Encryption Core

Kumar, A., Mehfuz, S., & Urooj, S. (2026) · Symmetry · doi:10.3390/sym18060897

Efficient Hardware Architectures for AES-128, AES-192, and AES-256 Encryption

Ashmawy, D., & Reyhani-Masoleh, A. (2026) · IEEE Transactions on Computers · doi:10.1109/tc.2026.3701703

FPGA DOSTU KOMPAKT VE VERİMLİ AES BENZERİ 8X8 S-KUTUSU

MALAL, A. (2023) · OpenMETU (Middle East Technical University)

Evaluation of AES Encryption Using Diverse S-Box Design Approaches

Sarada, V., Modi, T., Singh, S., & Hinge, S. (2025) · International Conference on Intelligent and Cloud Computing (ICoICC) · doi:10.1109/icoicc64033.2025.11052033

Circuit and system design for optimal lightweight AES encryption on FPGA

Wong, M. M., Wong, M. L. D., Zhang, C., & Hijazin, I. (2018) · DR-NTU (Nanyang Technological University) · Cited by 13 · see citing works

AES S-Box/ Inv S-Box Optimization Using FPGA Implementation

Hamzah, H., Ahmad, N. B., Jabbar, M. H., & Soon, C. F. (2017) · Journal of Telecommunication Electronic and Computer Engineering (JTEC) · Cited by 1 · see citing works

TECHNOLOGY FPGA IMPLEMENTATION OF A COMPACT AES ALGORITHM WITH S-BOX OPTIMIZATION

Lohiya, P. (2015)