The DOI matches its Crossref record, with a small difference in title or year; 4 of the 4 references it cites were found in a registry or an index.
Metastability behavior of mismatched CMOS flip-flops using state diagram analysis
Abstract
The effect on the metastability of the mismatch of FET parameters and load capacitances in a CMOS latch/flip-flop is analyzed. A novel method using state diagrams is proposed. On the state diagrams obtained by transient analysis of the latch, a straight line can be approximately drawn that defines two semiplanes, which precisely determine the latch final state. SPICE simulation results are shown for matched/mismatched flip-flops.
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“What's worse, these inaccuracies affecting the symmetry of the metastability will cause bias and decrease the entropy rate of the outputs bits of metastable circuit [67].”
From True Random Number Generators Using Electrical Noise (2019) · cites this paper as [67]
Citations
Cites
The behaviour of flip-flops used as synchronizers and prediction of their failure rate
Veendrick, H. J. M. (1980) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.1980.1051359 · Cited by 228
Metastability of CMOS latch/flip-flop
Kim, L.-S., & Dutton, R. W. (1990) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.58286 · Cited by 96
Analysis of mesastable operation in RS CMOS flip-flops
Kacprzak, T., & Albicki, A. (1987) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.1987.1052671 · Cited by 64
Optimization of CMOS arbiter and synchronizer circuits with submicrometer MOSFETs
Sakurai, T. (1988) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.340 · Cited by 62
Cited by
True Random Number Generators Using Electrical Noise
Gong, L., Zhang, J., Liu, H., Sang, L., & Wang, Y. (2019) · IEEE Access · doi:10.1109/access.2019.2939027 · Cited by 77
“What’s worse, these inaccuracies affecting the symmetry of the metastability will cause bias and decrease the entropy rate of the outputs bits of metastable circuit [67].”
BackgroundLightweight TRNG Based on Multiphase Timing of Bistables
Wieczorek, P. Z. (2016) · IEEE Transactions on Circuits and Systems I: Regular Papers · doi:10.1109/tcsi.2016.2555248 · Cited by 27
Dual‐metastability FPGA‐based true random number generator
Wieczorek, P. Z. (2013) · Electronics Letters · doi:10.1049/el.2012.4126 · Cited by 18
Metadata
- Authors
- van Noije, W. A. M., Liu, W. T., & Navarro, J.
- Venue
- Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93
- Publisher
- IEEE
- Published
- 2002
- Pages
- 27.7.1-27.7.4
- Cited by
- 9
- References
- 4
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- van Noije, W. A. M., Liu, W. T., & Navarro, J. (2002). Metastability behavior of mismatched CMOS flip-flops using state diagram analysis. Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93. https://doi.org/10.1109/cicc.1993.590809
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Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.
