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Garp: a MIPS processor with a reconfigurable coprocessor

Hauser, J.R., Wawrzynek, J.·2002·Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186)

Abstract

Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.

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Metadata

Authors
Hauser, J. R., & Wawrzynek, J.
Venue
Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186)
Published
2002-11-23
Pages
12-21
OpenAlex
W2165099691
Cited by
792
References
0
FWCI
52.12
Type
conference paper
Language
en
Open access
closed

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CoChat. (2026). Citation check: Garp: a MIPS processor with a reconfigurable coprocessor. https://app.cochat.ai/papers/10.1109/fpga.1997.624600
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Hauser, J. R., & Wawrzynek, J. (2002). Garp: a MIPS processor with a reconfigurable coprocessor. Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186). https://doi.org/10.1109/fpga.1997.624600

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Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.