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Compute Caches
Abstract
This paper presents the Compute Cache architecture that enables in-place computation in caches. Compute Caches uses emerging bit-line SRAM circuit technology to re-purpose existing cache elements and transforms them into active very large vector computational units. Also, it significantly reduces the overheads in moving data between different levels in the cache hierarchy. Solutions to satisfy new constraints imposed by Compute Caches such as operand locality are discussed. Also discussed are simple solutions to problems in integrating them into a conventional cache hierarchy while preserving properties such as coherence, consistency, and reliability. Compute Caches increase performance by 1.9× and reduce energy by 2.4× for a suite of data-centric applications, including text and database query processing, cryptographic kernels, and in-memory checkpointing. Applications with larger fraction of Compute Cache operations could benefit even more, as our micro-benchmarks indicate (54× throughput, 9× dynamic energy savings).
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Citations
Cited by
Memory devices and applications for in-memory computing
Sebastian, A., Le Gallo, M., Khaddam-Aljameh, R., & Eleftheriou, E. (2020) · Nature Nanotechnology · doi:10.1038/s41565-020-0655-z · Cited by 2,289
X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories
Agrawal, A., Jaiswal, A., Lee, C., & Roy, K. (2018) · IEEE Transactions on Circuits and Systems I: Regular Papers · doi:10.1109/tcsi.2018.2848999 · Cited by 325
Metadata
- Authors
- Aga, S., Jeloka, S., Subramaniyan, A., Narayanasamy, S., Blaauw, D., & Das, R.
- Venue
- 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)
- Publisher
- IEEE
- Published
- 2017-02
- Pages
- 481-492
- ISSN
- 1530-0897 (ISSN-L)
- OpenAlex
- W2613569094
- Cited by
- 324
- References
- 0
- FWCI
- 22.84
- Type
- conference paper
- Language
- en
- Open access
- closed
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- CoChat. (2026). Citation check: Compute Caches. https://app.cochat.ai/papers/10.1109/hpca.2017.21
- The paper
- Aga, S., Jeloka, S., Subramaniyan, A., Narayanasamy, S., Blaauw, D., & Das, R. (2017). Compute Caches. 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). https://doi.org/10.1109/hpca.2017.21
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Bibliographic data: Semantic Scholar, OpenAlex, Crossref.
Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.
