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X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories
Open accessAbstract
Silicon-based static random access memories (SRAM) and digital Boolean logic have been the workhorse of the state-of-the-art computing platforms. Despite tremendous strides in scaling the ubiquitous metal-oxide-semiconductor transistor, the underlying von-Neumann computing architecture has remained unchanged. The limited throughput and energy-efficiency of the state-of-the-art computing systems, to a large extent, result from the well-known von-Neumann bottleneck. The energy and throughput inefficiency of the von-Neumann machines have been accentuated in recent times due to the present emphasis on data-intensive applications such as artificial intelligence, machine learning, and cryptography. A possible approach towards mitigating the overhead associated with the von-Neumann bottleneck is to enable in-memory Boolean computations. In this paper, we present an augmented version of the conventional SRAM bit-cells, called the X-SRAM, with the ability to perform in-memory, vector Boolean computations, in addition to the usual memory storage operations. We propose at least six different schemes for enabling in-memory vector computations, including NAND, NOR, IMP (implication), XOR logic gates, with respect to different bit-cell topologies - the 8T cell and the 8+T Differential cell. In addition, we also present a novel `read-compute-store' scheme, wherein the computed Boolean function can be directly stored in the memory without the need of latching the data and carrying out a subsequent write operation. The feasibility of the proposed schemes has been verified using the predictive transistor models and detailed Monte-Carlo variation analysis. As an illustration, we also present the efficacy of the proposed in-memory computations by implementing advanced encryption standard algorithm on a non-standard von-Neumann machine wherein the conventional SRAM is replaced by X-SRAM. Our simulations indicated that up to 75% of memory accesses can be saved using the proposed techniques.
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Cites
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A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory
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Cited by
Xue, C.-X., Chiu, Y.-C., Liu, T.-W., Huang, T.-Y., Liu, J.-S., Chang, T.-W., Kao, H.-Y., Wang, J.-H., Wei, S.-Y., Lee, C.-Y., et al. (2020) · Nature Electronics · doi:10.1038/s41928-020-00505-5 · Cited by 181
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Metadata
- Authors
- Agrawal, A., Jaiswal, A., Lee, C., & Roy, K.
- Venue
- IEEE Transactions on Circuits and Systems I: Regular Papers
- Published
- 2018-12
- Volume
- 65
- Issue
- 12
- Pages
- 4219-4232
- ISSN
- 1549-8328 (ISSN-L)
- 1558-0806
- OpenAlex
- W2775637085
- Cited by
- 325
- References
- 17
- FWCI
- 8.56
- Type
- journal article
- Language
- en
- Open access
- green
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