A Novel Intelligent Power Module in Embedded Packaging with Low Parasitic Inductance and Low Thermal Resistance
Abstract
By combining embedding and 3D stacking techniques, a novel intelligent power module is introduced in this paper. The power stages are embedded and stacked in the organic substrates and the drivers are surface mounted on the board. The connection of gate drivers and power devices is conducted via copper wiring, leading to a shorter path and a smaller parasitic inductance. Specifically, the parasitic inductance of GS loop is decreased from 45 nH to 20 nH, reaching an almost 56% reduction. The SiC MOSFETs are stacked vertically to achieve half-bridge circuit and the inductance of DS loop is reduced from 5.4nH to 2.3 nH. Moreover, the power density is improved from 11.4 A/cm2to 18.2 A/cm2. It is worth to mention that the heat sinks are directly bonded to the module by insulation material with high thermal conductivity, thus optimizing the heat dissipation path and improving the Rjf performance significantly.
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Embedded packaging places power dies inside the printed circuit board, which lowers parasitic inductance and capacitance, reduces package height, and creates an efficient vertical thermal path.
“Embedded packaging places power dies inside the printed circuit board (PCB), which lowers parasitic inductance/capacitance, reduces package height, and creates an efficient vertical thermal path.”
From Thermal Management of Wide-Bandgap Power Semiconductors: Strategies and Challenges in SiC and GaN Power Devices (2025) · cites this paper as [47]
Embedded packaging provides inherent electromagnetic interference shielding and significantly improves robustness against thermal cycling and electrical overstress.
“The embedded paradigm also provides inherent electromagnetic interference (EMI) shielding and significantly improves robustness against thermal cycling and electrical overstress [29,45-49].”
From Thermal Management of Wide-Bandgap Power Semiconductors: Strategies and Challenges in SiC and GaN Power Devices (2025) · cites this paper as [47]
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Self-citationOptimized Power Modules for Silicon Carbide mosfet
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A novel heat dissipation structure for PSiP package
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Han, G., Kim, J., Park, S., & Bae, W. (2025) · Electronics · doi:10.3390/electronics14214193 · Cited by 34 · see citing works
- Authors
- Wang, J., Liu, Z., Peng, H., & Ren, X.
- Affiliations
- Shanghai Huawei Digital Power Technologies Co., Ltd.,Shanghai,China
- Venue
- 2024 25th International Conference on Electronic Packaging Technology (ICEPT)
- Publisher
- IEEE
- Published
- 2024-08-07
- Pages
- 1-4
- OpenAlex
- W4402743222
- Cited by
- 4
- References
- 7
- Citations by year
- 2026: 1 · 2025: 3
- FWCI
- 3.06
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- International Conference on Electronic Packaging Technology (ICEPT) (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Silicon Carbide Semiconductor Technologies
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced DC-DC Converters
- Physical Sciences › Engineering › Electrical and Electronic Engineering › 3D IC and TSV technologies
- Keywords
- intelligent power module, 3D stacking, parasitic inductance reduction, thermal resistance, SiC MOSFET, half-bridge circuit, organic substrates, gate driver, power density
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