Interconnection-Varied Warpage Modeling of Sintered-Nanosilver-Connected Power Modules with a Heatsink Considering Time Sequence Efforts
Abstract
The nanosilver sintering techniques are gaining increasing popularity in the packaging of wide bandgap (WBG) semiconductors for their superior characteristics of high electrical conductivity, low interconnection thermal resistance, and high working reliability. However, there is residual deformation and stress after sintering, which will not only reduce the module's heat dissipation capacity but also shorten its operating life. Therefore, the investigation of the thermal residual stresses and deformations induced by the sintering processes is a key issue in packaging a module. Since the nanosilver paste maintains solid throughout the sintering processes and only changes on the interface connection, it is difficult to accurately simulate the influences caused by the sintering processes on the residual stress and warpage using conventional numerical models with element-birth-and-death. In this paper, a time sequence method with the variation in interconnection is proposed to model the deformations and stresses generated in the nanosilver sintering processes. In the proposed method, the nanosilver layer is divided into several solder blocks, and the connection processes are realized by varying the interconnection situations of the bricks and the connecting components. The proposed methodologies are used in simulating the warpage and residual stresses of a heatsink that is sintered with three modules, and the warpage characteristics of the heatsink are discussed. The simulation method can guide the processing optimization for mitigating the warpage caused by the packing sequence.
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Cu sintering is effective at high temperature, though conductivity degradation and residual-stress sensitivity remain process-dependent.
“Cu sintering is effective at high temperature, though conductivity degradation and residual-stress sensitivity remain process-dependent [84].”
From Thermal Management of Wide-Bandgap Power Semiconductors: Strategies and Challenges in SiC and GaN Power Devices (2025) · cites this paper as [84]
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Han, G., Kim, J., Park, S., & Bae, W. (2025) · Electronics · doi:10.3390/electronics14214193 · Cited by 34 · see citing works
- Authors
- Zhu, G., Zhang, L., Hou, Z., Wang, Y., Liang, L., & Mei, Y.
- Affiliations
- Tiangong University (CN)
- Huawei Technologies (China) (CN)
- School of Electronic Engineering Tiangong University,Tianjin,China
- Venue
- 2024 25th International Conference on Electronic Packaging Technology (ICEPT)
- Publisher
- IEEE
- Published
- 2024-08-07
- Pages
- 01-05
- OpenAlex
- W4402743636
- Cited by
- 3
- References
- 18
- Citations by year
- 2026: 1 · 2025: 2
- FWCI
- 2.30
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- International Conference on Electronic Packaging Technology (ICEPT) (publishedVersion)
- Funders
- National Natural Science Foundation of China (52177189)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Electronic Packaging and Soldering Technologies
- Physical Sciences › Engineering › Electrical and Electronic Engineering › 3D IC and TSV technologies
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Silicon Carbide Semiconductor Technologies
- Keywords
- thermal residual stress, power modules, heat sinks, heat dissipation
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