The DOI matches its Crossref record; 9 of the 9 references it cites were found in a registry or an index.
A 307-fps 351.7-GOPs/W Deep Learning FPGA Accelerator for Real-Time Scene Text Recognition
Abstract
FPGA-based deep learning accelerator has become important for high throughput and low power inference at edges. In this paper, we have developed a computing-in-memory (CIM) accelerator using the binary SegNet (BSEG) for real-time scene text recognition (STR) at edges. The accelerator can perform highly efficient pixel-wise character classification under CIM architecture with massive bit-level parallelism as well as optimized pipeline for low latency at critical path. The BSEG is obtained during training with a small model size of 2.1MB as well as a high classification accuracy over 90% on ICDAR-03 and ICDAR-13 datasets. The RTL-level realized FPGA-accelerator can process the STR with an energy-efficiency of 351.7 GOPs/W and a throughput of 307 fps for processing one frame of 128×32 pixels in latency of 3.875 ms.
Overview
Integrity signals
Registry
Cites
Statistics
Verification
Claims the paper makes
Claims other papers make about this one
Each is checked against this paper’s own text: does it say what the citing paper says it does?
The experimental results show that a throughput of 307.7 fps with interval of 3.25 ms and a latency of 3.875 ms are achieved with the trained binary quantization and computing-in-memory architecture.
“The experimental results show that a throughput of 307.7 fps with interval of 3.25 ms and a latency of 3.875 ms are achieved with the trained binary quantization and computingin-memory architecture.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [66]
The real-time recognition system with FPGA was able to improve 14, 19 and 3 times better in term of area on chip usage whereas 57, 24 and 8 times more energy efficient when compared to other models that use GPU as reference.
“In conclusion, the real-time recognition system with FPGA was able to improve 14, 19 and 3 times better in term of area on chip usage whereas 57, 24 and 8 times more energy efficient when compared to other models that use GPU as reference [66].”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [66]
Another example of object detection application is real-time scene text recognition.
“In addition, another example of object detection application is real-time scene text recognition.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [66]
The FPGA-based encoder-decoder accelerator consumes 8.95 W of dynamic power, equivalent to energy efficiency of 351.7-GOPs/W.
“The FPGA-based encoder-decoder accelerator consumes 8.95 W of dynamic power, equivalent to energy efficiency of 351.7-GOPs/W.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [66]
Citations
Cites
Shi, B., Bai, X., & Yao, C. (2016) · IEEE Transactions on Pattern Analysis and Machine Intelligence · doi:10.1109/tpami.2016.2646371 · Cited by 3,319
Going Deeper with Embedded FPGA Platform for Convolutional Neural Network
Qiu, J., Wang, J., Yao, S., Guo, K., Li, B., Zhou, E., Yu, J., Tang, T., Xu, N., Song, S., et al. (2016) · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · doi:10.1145/2847263.2847265 · Cited by 1,290
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference
Umuroglu, Y., Fraser, N. J., Gambardella, G., Blott, M., Leong, P., Jahre, M., & Vissers, K. (2017) · Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays · doi:10.1145/3020078.3021744 · Cited by 1,189
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks
Suda, N., Chandra, V., Dasika, G. S., Mohanty, A., Ma, Y., Vrudhula, S. B. K., Seo, J.-S., & Cao, Y. K. (2016) · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · doi:10.1145/2847263.2847276 · Cited by 556
Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs
Zhao, R., Song, W., Zhang, W., Xing, T., Lin, J.-H., Srivastava, M. B., Gupta, R. K., & Zhang, Z. (2017) · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · doi:10.1145/3020078.3021741 · Cited by 437
Rosetta: Large Scale System for Text Detection and Recognition in Images
Borisyuk, F., Gordo, A., & Sivakumar, V. (2018) · Proceedings of the 24th ACM SIGKDD International Conference on Knowledge Discovery & Data Mining · doi:10.1145/3219819.3219861 · Cited by 353
STAR-Net: A SpaTial Attention Residue Network for Scene Text Recognition
Liu, W., Chen, C., Wong, K. K., Su, Z., & Han, J. (2016) · British Machine Vision Conference (BMVC) · doi:10.5244/c.30.43 · Cited by 280
SqueezedText: A Real-Time Scene Text Recognition by Binary Convolutional Encoder-Decoder Network
Liu, Z., Li, Y., Ren, F., Goh, W. L., & Yu, H. (2018) · Proceedings of the AAAI Conference on Artificial Intelligence · doi:10.1609/aaai.v32i1.12252 · Cited by 98
Self-citationLi, Y., Liu, Z., Liu, W., Jiang, Y. S., Wang, Y., Goh, W. L., Yu, H., & Ren, F. (2018) · IEEE Transactions on Industrial Electronics · doi:10.1109/tie.2018.2875643 · Cited by 20
Self-citation
Flagged first, then by citations
Cited by
Sorted by citations
Embedded Intelligence on FPGA: Survey, Applications and Challenges
Seng, K. P., Lee, P. J., & Ang, L. M. (2021) · Electronics · doi:10.3390/electronics10080895 · Cited by 105
“Encoder–decoder neural network [66] (Reprinted with permission from ref.”
BackgroundMethodInfluential
Metadata
- Authors
- Zhao, S., An, F., & Yu, H.
- Affiliations
- Southern University of Science and Technology (CN)
- Venue
- 2019 International Conference on Field-Programmable Technology (ICFPT)
- Publisher
- IEEE
- Published
- 2019-12
- Volume
- 2019
- Pages
- 263-266
- OpenAlex
- W3003348917
- Cited by
- 8
- References
- 9
- Citations by year
- 2025: 1 · 2023: 1 · 2022: 2 · 2021: 2 · 2020: 2
- FWCI
- 0.49
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- International Conference on Field-Programmable Technology (FPT) (publishedVersion)
- IEEE Conference Proceedings
- Topics
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Embedded Systems and FPGA Applications
- Keywords
- FPGA accelerator, scene text recognition, in-memory computing, edge inference, energy efficiency, RTL design
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
Are you an author, or do you see a problem with this page? Request a review
