Prototyping and Evaluation of SiC Half Bridge Circuit Using Power Device Embedded Module Process Towards Future Three Dimensional Packaging
Abstract
Recently WBG (Wide Band Gap) power semiconductors such as SiC and GaN, which have been attracting attention, are being applied in power electronics field because of their high switching speed and low losses compared to existing Si power devices. SiC is spreading from industrial applications to main traction systems of N700S SHINKANSEN bullet trains, and GaN is spreading to low-voltage applications such as AC adapters, DC/DC converters and LED drivers etc. . On the other hand, there are problems such as surge noise due to current path stray inductance Ls by high current reduction rate, di/dt, at turn-off. To reduce the turn-off voltage surge, it is necessary to optimize structure of main current path to minimize Ls. In optimizing the structure, loop inductance can be reduced by forming a return path in which current distribution could cancels leakage magnetic flux. However, depending on the switching mode of the power converter topology, such as a three phase inverter, the main current may not always be a return path that cancels the leakage magnetic flux. This time, in order to confirm the usefulness of Power Device Embedded Module (POWER DEM) packaging process, a prototype of SiC bare die embedded half-bridge circuit has been prototyped. Inductance analyzed results of circuit structure using ANSYS Q3D Extractor® before prototyping, have been comparatively evaluated. As a result, loop inductance was 5.5 nH in Q3D analysis, 3.6 nH in impedance analyzer, and calculated inductance from actual surge voltage was 10.03 nH. Finally, turn-off voltage surge, turn-on loss, turn-off loss, turn-on time and turn-off time have been reduced approximately 40 % to 80 % compared to similar half bridge circuit using conventional TO-247 packages. Further works are to optimize current path constructions for actual cases of circuit topologies i.e. three phase inverter etc., modeling of three dimensional structure including dielectric insulating material and analyze methods.
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Embedded packaging places power dies inside the printed circuit board, which lowers parasitic inductance and capacitance, reduces package height, and creates an efficient vertical thermal path.
“Embedded packaging places power dies inside the printed circuit board (PCB), which lowers parasitic inductance/capacitance, reduces package height, and creates an efficient vertical thermal path.”
From Thermal Management of Wide-Bandgap Power Semiconductors: Strategies and Challenges in SiC and GaN Power Devices (2025) · cites this paper as [45]
Embedded packaging provides inherent electromagnetic interference shielding and significantly improves robustness against thermal cycling and electrical overstress.
“The embedded paradigm also provides inherent electromagnetic interference (EMI) shielding and significantly improves robustness against thermal cycling and electrical overstress [29,45-49].”
From Thermal Management of Wide-Bandgap Power Semiconductors: Strategies and Challenges in SiC and GaN Power Devices (2025) · cites this paper as [45]
Double-sided cooling, embedded packaging, and interleaved planar structures mitigate current imbalance across parallel dies and reduce parasitics.
“DSC, embedded packaging, and interleaved planar structures mitigate current imbalance across parallel dies and reduce parasitics [10,40,45,82].”
From Thermal Management of Wide-Bandgap Power Semiconductors: Strategies and Challenges in SiC and GaN Power Devices (2025) · cites this paper as [45]
Cites
Performance Comparison Between Surface-mount and Embedded Power Modules
Weis, G. (2019) · Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) · doi:10.4071/2380-4491-2019-dpc-presentation_tp3_052 · Cited by 2 · see citing works
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Han, G., Kim, J., Park, S., & Bae, W. (2025) · Electronics · doi:10.3390/electronics14214193 · Cited by 34 · see citing works
“• High-frequency DC/DC • Integrated power systems [45] Interleaved Planar • Thermal coupling reduction: ∼ 57% • L p as low as 3.8nH [40] • Balances current/temperature in parallel devices • Mitigates 2D thermal coupling [40] • High structural complexity • Potential manufacturability challenges •…”
- Authors
- Nakamura, K., Shigematsu, K., Imaoka, J., & Yamamoto, M.
- Affiliations
- Institute of Materials and Systems for Sustainability, Nagoya University (JP)
- ORCID
- Imaoka, Jun
- Venue
- 2023 IEEE CPMT Symposium Japan (ICSJ)
- Publisher
- IEEE
- Published
- 2023-11-15
- Pages
- 196-199
- OpenAlex
- W4389575376
- Cited by
- 1
- References
- 1
- Citations by year
- 2025: 1
- FWCI
- 0.49
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- IEEE CPMT Symposium Japan (ICSJ) (publishedVersion)
- Funders
- Semiconductor Packaging Research Institute of Fukuoka University
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Silicon Carbide Semiconductor Technologies
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Electromagnetic Compatibility and Noise Suppression
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced DC-DC Converters
- Keywords
- silicon carbide power devices, half-bridge circuit, wide bandgap semiconductors, loop inductance, magnetic flux leakage, 3D packaging
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