Cited by 1Silicon Carbide Semiconductor TechnologiesElectromagnetic Compatibility and Noise SuppressionAdvanced DC-DC Converters

Prototyping and Evaluation of SiC Half Bridge Circuit Using Power Device Embedded Module Process Towards Future Three Dimensional Packaging

Nakamura, Kazuhito, Shigematsu, Koichi, Imaoka, Jun, Yamamoto, Masayoshi·2023·2023 IEEE CPMT Symposium Japan (ICSJ)

Abstract

Recently WBG (Wide Band Gap) power semiconductors such as SiC and GaN, which have been attracting attention, are being applied in power electronics field because of their high switching speed and low losses compared to existing Si power devices. SiC is spreading from industrial applications to main traction systems of N700S SHINKANSEN bullet trains, and GaN is spreading to low-voltage applications such as AC adapters, DC/DC converters and LED drivers etc. . On the other hand, there are problems such as surge noise due to current path stray inductance Ls by high current reduction rate, di/dt, at turn-off. To reduce the turn-off voltage surge, it is necessary to optimize structure of main current path to minimize Ls. In optimizing the structure, loop inductance can be reduced by forming a return path in which current distribution could cancels leakage magnetic flux. However, depending on the switching mode of the power converter topology, such as a three phase inverter, the main current may not always be a return path that cancels the leakage magnetic flux. This time, in order to confirm the usefulness of Power Device Embedded Module (POWER DEM) packaging process, a prototype of SiC bare die embedded half-bridge circuit has been prototyped. Inductance analyzed results of circuit structure using ANSYS Q3D Extractor® before prototyping, have been comparatively evaluated. As a result, loop inductance was 5.5 nH in Q3D analysis, 3.6 nH in impedance analyzer, and calculated inductance from actual surge voltage was 10.03 nH. Finally, turn-off voltage surge, turn-on loss, turn-off loss, turn-on time and turn-off time have been reduced approximately 40 % to 80 % compared to similar half bridge circuit using conventional TO-247 packages. Further works are to optimize current path constructions for actual cases of circuit topologies i.e. three phase inverter etc., modeling of three dimensional structure including dielectric insulating material and analyze methods.

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Crossref · 10.1109/icsj59341.2023.10339574

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Authors
Nakamura, K., Shigematsu, K., Imaoka, J., & Yamamoto, M.
Affiliations
Institute of Materials and Systems for Sustainability, Nagoya University (JP)
Venue
2023 IEEE CPMT Symposium Japan (ICSJ)
Publisher
IEEE
Published
2023-11-15
Pages
196-199
OpenAlex
W4389575376
Cited by
1
References
1
Citations by year
2025: 1
FWCI
0.49
Type
conference paper
Language
en
Open access
closed
Locations
IEEE CPMT Symposium Japan (ICSJ) (publishedVersion)
Funders
Semiconductor Packaging Research Institute of Fukuoka University
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Silicon Carbide Semiconductor Technologies
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Electromagnetic Compatibility and Noise Suppression
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced DC-DC Converters
Keywords
silicon carbide power devices, half-bridge circuit, wide bandgap semiconductors, loop inductance, magnetic flux leakage, 3D packaging

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