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Interconnect scaling-the real limiter to high performance ULSI
Abstract
Reducing interconnect pitch improves layout density, but degrades interconnect RC delay. Increasing metal aspect ratio (thickness/width) improves RC delay, but maximum benefits are achieved at an aspect ratio of /spl sim/2. Adding more interconnect layers improves density and performance, but practical limits are reached in just a few generations. New conductor and dielectric materials and improved circuit design techniques will be needed to meet future ULSI interconnect requirements.
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Citations
Cited by
Limits on fundamental limits to computation
Markov, I. L. (2014) · Nature · doi:10.1038/nature13570 · Cited by 494
DIVA: a reliable substrate for deep submicron microarchitecture design
Austin, T. M. (2003) · MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture · doi:10.1109/micro.1999.809458 · Cited by 380
Lanzerotti, M. Y., Fiorenza, G., & Rand, R. A. (2005) · IBM Journal of Research and Development · doi:10.1147/rd.494.0777 · Cited by 47
Metadata
- Authors
- Bohr, M. T.
- Venue
- Proceedings of International Electron Devices Meeting
- Publisher
- IEEE
- Published
- 2002-11-19
- Pages
- 241-244
- ISSN
- 0163-1918 (ISSN-L)
- OpenAlex
- W2120062652
- Cited by
- 552
- References
- 0
- FWCI
- 120.55
- Type
- conference paper
- Language
- en
- Open access
- closed
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- CoChat. (2026). Citation check: Interconnect scaling-the real limiter to high performance ULSI. https://app.cochat.ai/papers/10.1109/iedm.1995.499187
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- Bohr, M. T. (2002). Interconnect scaling-the real limiter to high performance ULSI. Proceedings of International Electron Devices Meeting. https://doi.org/10.1109/iedm.1995.499187
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Bibliographic data: Semantic Scholar, OpenAlex, Crossref.
Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.