Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition
Abstract
The ability to learn from few examples, known as one-shot learning, is a hallmark of human cognition. Hyperdimensional (HD) computing is a brain-inspired computational framework capable of one-shot learning, using random binary vectors with high dimensionality. Device-architecture co-design of HD cognitive computing systems using 3D VRRAM/CMOS is presented for language recognition. Multiplication-addition-permutation (MAP), the central operations of HD computing, are experimentally demonstrated on 4-layer 3D VRRAM/FinFET as non-volatile in-memory MAP kernels. Extensive cycle-to-cycle (up to 1012cycles) and wafer-level device-to-device (256 RRAMs) experiments are performed to validate reproducibility and robustness. For 28-nm node, the 3D in-memory architecture reduces total energy consumption by 52.2% with 412 times less area compared with LP digital design (using registers as memory), owing to the energy-efficient VRRAM MAP kernels and dense connectivity. Meanwhile, the system trained with 21 samples texts achieves 90.4% accuracy recognizing 21 European languages on 21,000 test sentences. Hard-error analysis shows the HD architecture is amazingly resilient to RRAM endurance failures, making the use of various types of RRAMs/CBRAMs (1k ~ 10M endurance) feasible.
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In-memory computing is widely studied as an energy-efficient approach for hyperdimensional computing.
“Therefore, in-memory computing is widely studied as an energy-efficient approach for hyperdimensional computing [135, 140,141,142].”
From Brain-inspired computing systems: a systematic literature review (2024) · cites this paper as [142]
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“Therefore, in-memory computing is widely studied as an energy-efficient approach for hyperdimensional computing [135, 140–142].”
Method
- Authors
- Li, H., Wu, T. F., Rahimi, A., Li, K.-S., Rusch, M., Lin, C.-H., Hsu, J.-L., Sabry, M. M., Eryilmaz, S. B., Sohn, J., Chiu, W.-C., Chen, M.-C., Wu, T.-T., Shieh, J.-M., Yeh, W.-K., Rabaey, J. M., Mitra, S., & Wong, H.-S. P.
- Affiliations
- Stanford University (US)
- University of California, Berkeley (US)
- ORCID
- Venue
- 2016 IEEE International Electron Devices Meeting (IEDM)
- Publisher
- IEEE
- Published
- 2016-12
- Pages
- 16.1.1-16.1.4
- ISSN
- 0163-1918 (ISSN-L)
- OpenAlex
- W2583857261
- Cited by
- 136
- References
- 5
- Citations by year
- 2026: 3 · 2025: 8 · 2024: 12 · 2023: 14 · 2022: 19 · 2021: 26 · 2020: 10 · 2019: 15 · 2018: 19 · 2017: 9 · 2016: 1
- FWCI
- 20.64
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- Technical digest - International Electron Devices Meeting/Technical digest (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Keywords
- hyperdimensional computing, in-memory computing, one-shot learning, language identification, non-volatile memory, FinFET, energy efficiency, error resilience, neuromorphic computing, cognitive computing
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