Cited by 55Parallel Computing and Optimization TechniquesAdvanced Memory and Neural ComputingAdvanced Neural Network Applications

The DOI matches its Crossref record; 1 of the 1 references it cites were found in a registry or an index.

Design Considerations for Efficient Deep Neural Networks on Processing-in-Memory Accelerators

Open access
Yang, Tien-Ju, Sze, Vivienne·2019·2019 IEEE International Electron Devices Meeting (IEDM)

Abstract

This paper describes various design considerations for deep neural networks that enable them to operate efficiently and accurately on processing-in-memory accelerators. We highlight important properties of these accelerators and the resulting design considerations using experiments conducted on various state-of-the- art deep neural networks with the large-scale ImageNet dataset.

Overview

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Registry

Crossref · 10.1109/iedm19573.2019.8993662

Cites

1 of 1 references verified0 citation errors · 0 not checkable

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  • Little or no loss in accuracy can be achieved when using binary weights for some earlier deep convolutional networks, such as AlexNet or VGG.

    “though little or no loss in accuracy can be achieved when using binary weights for some of the earlier (very redundant) deep convolutional networks, such as AlexNet or VGG”

    From 4K-memristor analog-grade passive crossbar circuit (2021) · cites this paper as [49]

  • 4 to 8 bits of precision for both weights and activations might be necessary for the most advanced image classifiers.

    “4 to 8 bits of precision for both weights and activations might be necessary for the most advanced image classifiers49”

    From 4K-memristor analog-grade passive crossbar circuit (2021) · cites this paper as [49]

Citations

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Research works printed but not linked: 6

  1. 10.3389/fnins.2016.00333 · DOI · Paper page
  2. 10.1109/DAC.2018.8465834 · DOI · Paper page
  3. 10.1145/3007787.3001177 · DOI · Paper page
  4. zagoruyko, 2017, Wide Residual Networks, British Machine Vision Conference
  5. 10.1109/JPROC.2018.2790840 · DOI · Paper page
  6. yang, 2018, Understanding the Limitations of Existing Energy-Efficient Design Approaches for Deep Neural Networks, SysML Conference

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Metadata

Authors
Yang, T.-J., & Sze, V.
Affiliations
Massachusetts Institute of Technology (US)
Venue
2019 IEEE International Electron Devices Meeting (IEDM)
Publisher
IEEE
Published
2019-12
Pages
22.1.1-22.1.4
ISSN
0163-1918 (ISSN-L)
OpenAlex
W3006248624
Cited by
55
References
1
Citations by year
2026: 2 · 2025: 2 · 2024: 8 · 2023: 8 · 2022: 14 · 2021: 13 · 2020: 8
FWCI
6.75
Type
conference paper
Language
en
Open access
Locations
  • Technical digest - International Electron Devices Meeting/Technical digest (publishedVersion)
  • arXiv (Cornell University) (submittedVersion)
  • DSpace@MIT (Massachusetts Institute of Technology) (submittedVersion, cc-by-nc-sa)
  • arXiv (Cornell University)
Funders
  • National Science Foundation (1639921, E2CDA)
  • Quest for Intelligence, Massachusetts Institute of Technology
Topics
  • Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
  • Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
Keywords
in-memory computing, neural network accelerators, deep neural network design, energy efficiency, ImageNet, accelerator architecture

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