The DOI matches its Crossref record; 7 of the 7 references it cites were found in a registry or an index.
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory
Abstract
Processing-in-memory (PIM) is a promising solution to address the "memory wall" challenges for future computer systems. Prior proposed PIM architectures put additional computation logic in or near memory. The emerging metal-oxide resistive random access memory (ReRAM) has showed its potential to be used for main memory. Moreover, with its crossbar array structure, ReRAM can perform matrix-vector multiplication efficiently, and has been widely studied to accelerate neural network (NN) applications. In this work, we propose a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory. In PRIME, a portion of ReRAM crossbar arrays can be configured as accelerators for NN applications or as normal memory for a larger memory space. We provide microarchitecture and circuit designs to enable the morphable functions with an insignificant area overhead. We also design a software/hardware interface for software developers to implement various NNs on PRIME. Benefiting from both the PIM architecture and the efficiency of using ReRAM for NN computation, PRIME distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving. Our experimental results show that, compared with a state-of-the-art neural processing unit design, PRIME improves the performance by ~2360x and the energy consumption by ~895x, across the evaluated machine learning benchmarks.
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Gradient-based learning applied to document recognition
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Training and operation of an integrated neuromorphic network based on metal-oxide memristors
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Lee, M.-J., Lee, C. B., Lee, D., Lee, S. R., Chang, M., Hur, J. H., Kim, Y.-B., Kim, C.-J., Seo, D. H., Seo, S., et al. (2011) · Nature Materials · doi:10.1038/nmat3070 · Cited by 2,228
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ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars
Shafiee, A., Nag, A., Muralimanohar, N., Balasubramonian, R., Strachan, J. P., Hu, M., Williams, R. S., & Srikumar, V. (2016) · 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) · doi:10.1109/isca.2016.12 · Cited by 775
Pattern classification by memristive crossbar circuits using ex situ and in situ training
Alibart, F., Zamanidoost, E., & Strukov, D. B. (2013) · Nature Communications · doi:10.1038/ncomms3072 · Cited by 642
High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm
Alibart, F., Gao, L., Hoskins, B. D., & Strukov, D. B. (2012) · Nanotechnology · doi:10.1088/0957-4484/23/7/075201 · Cited by 557
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Zhang, W., Gao, B., Tang, J., Yao, P., Yu, S., Chang, M.-F., Yoo, H.-J., Qian, H., & Wu, H. (2020) · Nature Electronics · doi:10.1038/s41928-020-0435-7 · Cited by 892
ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars
Shafiee, A., Nag, A., Muralimanohar, N., Balasubramonian, R., Strachan, J. P., Hu, M., Williams, R. S., & Srikumar, V. (2016) · 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) · doi:10.1109/isca.2016.12 · Cited by 775
Hardware implementation of memristor-based artificial neural networks
Aguirre, F., Sebastian, A., Le Gallo, M., Song, W., Wang, T., Yang, J. J., Lu, W., Chang, M.-F., Ielmini, D., Yang, Y., et al. (2024) · Nature Communications · doi:10.1038/s41467-024-45670-9 · Cited by 564
Self-citation
Metadata
- Authors
- Chi, P., Li, S., Xu, C., Zhang, T., Zhao, J., Liu, Y., Wang, Y., & Xie, Y.
- Venue
- 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)
- Publisher
- IEEE
- Published
- 2016-06
- Pages
- 27-39
- OpenAlex
- W4254672563
- Cited by
- 573
- References
- 7
- FWCI
- 83.39
- Type
- conference paper
- Language
- en
- Open access
- closed
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