FPGA-Based Convolutional Neural Network Architecture with Reduced Parameter Requirements
Abstract
The success of deep learning has fast paced the evolution of current technology at unprecedented rate. In particular, deep convolutional neural networks (CNNs) has gained a lot of attention due to their extraordinary performance in a wide range of computer vision applications. While the performance of CNNs has been excellent, their implementation complexity has, however, always posed a challenge due to their computational and memory access intensive nature of CNNs especially for resource constrained embedded platforms. In this paper, we propose a novel reduced-parameter CNN architecture that can be used for image classification applications, which results in a significant network model size reduction. Our reduction method, inspired by SqueezeNet, replaces convolutional layer kernels with smaller sized kernels and removes all the fully connected layers other than the last classifying layer. The proposed architecture results in less computational complexity when deployed in hardware. We implemented the proposed architecture by fitting all trained network parameters on-chip using Xilinx Vivado targeting Zynq XC7Z020-1CLG484C FPGA device. The proposed architecture has 11.2× less parameters and has an improvement of 2.8× Area-Delay Product, compared to LeNet, resulting in an efficient hardware deployment.
Integrity signals
Registry
Cites
Statistics
Claims the paper makes
Claims other papers make about this one
Each is checked against this paper’s own text: does it say what the citing paper says it does?
Using the fire module technique reduced parameters by 11.2 times fewer than a standard network without impacting classification accuracy.
“By using this fire module technique, it was able to reduce the parameter by 11.2 times fewer than standard network without impacting classification accuracy [28].”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [28]
Cites
ImageNet classification with deep convolutional neural networks
Krizhevsky, A., Sutskever, I., & Hinton, G. E. (2017) · Communications of the ACM · doi:10.1145/3065386 · Cited by 112,155 · see citing works
SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and <0.5MB model size
Iandola, F. N., Han, S., Moskewicz, M. W., Ashraf, K., Dally, W. J., & Keutzer, K. (2016) · arXiv · doi:10.48550/arxiv.1602.07360 · Cited by 6,201 · see citing works
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
Zhang, C., Li, P., Sun, G., Guan, Y., Xiao, B., & Cong, J. (2015) · Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays · doi:10.1145/2684746.2689060 · Cited by 2,158 · see citing works
Exploiting Linear Structure Within Convolutional Networks for Efficient Evaluation
Denton, R., Zaremba, W., Bruna, J., LeCun, Y., & Fergus, R. (2014) · arXiv · doi:10.48550/arxiv.1404.0736 · Cited by 1,414 · see citing works
Going Deeper with Embedded FPGA Platform for Convolutional Neural Network
Qiu, J., Wang, J., Yao, S., Guo, K., Li, B., Zhou, E., Yu, J., Tang, T., Xu, N., Song, S., et al. (2016) · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · doi:10.1145/2847263.2847265 · Cited by 1,268 · see citing works
Object Recognition with Gradient-Based Learning
LeCun, Y., Haffner, P., Bottou, L., & Bengio, Y. (1999) · Lecture Notes in Computer Science · doi:10.1007/3-540-46805-6_19 · Cited by 947 · see citing works
Shafique, M., Theocharides, T., Bouganis, C.-S., Hanif, M. A., Khalid, F., Hafiz, R., & Rehman, S. (2018) · Design, Automation, and Test in Europe · doi:10.23919/date.2018.8342120 · Cited by 106 · see citing works
Self-citationAn FPGA-based accelerator implementation for deep convolutional neural networks
Zhou, Y., & Jiang, J. (2015) · International Conference on Computer Science and Network Technology (ICCSNT) · doi:10.1109/iccsnt.2015.7490869 · Cited by 78 · see citing works
Shafique, M., Hafiz, R., Javed, M. U., Abbas, S., Sekanina, L., Vašíček, Z., & Mrázek, V. (2017) · IEEE Computer Society Annual Symposium on VLSI · doi:10.1109/isvlsi.2017.124 · Cited by 55 · see citing works
Self-citationA fast FPGA-based deep convolutional neural network using pseudo parallel memories
Hailesellasie, M., & Hasan, S. R. (2017) · doi:10.1109/iscas.2017.8050317 · Cited by 12 · see citing works
Self-citation
Flagged first, then by citations
Cited by
Sorted by citations
Embedded Intelligence on FPGA: Survey, Applications and Challenges
Seng, K. P., Lee, P. J., & Ang, L. M. (2021) · Electronics · doi:10.3390/electronics10080895 · Cited by 105 · see citing works
“2 times fewer than standard network without impacting classification accuracy [28].”
BackgroundInfluentialLi, S., Luo, Y., Sun, K., Yadav, N., & Choi, K. K. (2020) · IEEE Access · doi:10.1109/access.2020.3000009 · Cited by 75 · see citing works
- Authors
- Hailesellasie, M., Hasan, S. R., Khalid, F., Wad, F. A., & Shafique, M.
- Affiliations
- Tennessee Technological University (US)
- TU Wien (AT)
- United Arab Emirates University (AE)
- Venue
- 2018 IEEE International Symposium on Circuits and Systems (ISCAS)
- Publisher
- IEEE
- Published
- 2018-05
- Pages
- 1-5
- ISSN
- 0271-4302 (ISSN-L)
- OpenAlex
- W2801550278
- Cited by
- 38
- References
- 10
- Citations by year
- 2026: 2 · 2025: 2 · 2024: 7 · 2023: 4 · 2022: 5 · 2021: 4 · 2020: 10 · 2019: 4
- FWCI
- 1.36
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- IEEE International Symposium on Circuits and Systems proceedings (publishedVersion)
- Topics
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Embedded Systems and FPGA Applications
- Keywords
- convolutional neural network architecture, FPGA implementation, parameter reduction, image classification, hardware resource efficiency, area-delay product, embedded vision, Xilinx Zynq
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
Are you an author, or do you see a problem with this page? Request a review
