A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS
Abstract
An 8 b SAR ADC is presented. The 90 nm CMOS prototype achieves an ENOB of 7.8 b at a sampling frequency of 10.24 MS/S. The use of asynchronous dynamic CMOS logic, custom-designed capacitors, an internal common-mode shift and low-leakage design techniques results in a power consumption of 69 ¿W from a 1 V supply. The corresponding FoM equals 30 fJ/Conversion-step and is maintained down to 10 kS/s.
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Because the conversion interval and the operations performed in it do not scale with sampling frequency, power consumption is expected to have an almost linear relation with sampling frequency.
“Since the size of this time interval and the amount of operations performed in it do not scale with the sampling frequency, it is expected an almost linear relation between power consumption and sampling frequency [8].”
From A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS (2021) · cites this paper as [8]
Asynchronous SAR ADCs require only one clock signal to control sampling, which relaxes clock distribution requirements.
“On the other hand, asynchronous SAR ADCs [7,8] require only one clock signal to control the sampling.This feature relaxes the clock distribution requirements.”
From A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS (2021) · cites this paper as [8]
A custom combinational asynchronous SAR logic based on the circuit described in [8], with modifications to support the merged capacitor switching scheme, allows manual device placement, presents reduced power consumption, and uses only one clock source.
“In this work, a custom combinational asynchronous SAR logic, based on the circuit described in [8], with modifications to support the merged capacitor switching scheme was employed.This asynchronous logic allows a ''manual'' device placement, presents reduced power consumption and makes use of only one clock source.”
From A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS (2021) · cites this paper as [8]
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A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS
Campos, A. L., Navarro, J., Luppe, M., & de Lima, E. R. (2021) · Analog Integrated Circuits and Signal Processing · doi:10.1007/s10470-020-01742-6 · Cited by 8 · see citing works
- Authors
- Harpe, P., Zhou, C., Wang, X., Dolmans, G., & de Groot, H.
- Affiliations
- Imec the Netherlands (NL)
- Venue
- 2010 IEEE International Solid-State Circuits Conference - (ISSCC)
- Publisher
- IEEE
- Published
- 2010-02
- Pages
- 388-389
- ISSN
- 0193-6530 (ISSN-L)
- OpenAlex
- W1974931639
- Cited by
- 96
- References
- 0
- Citations by year
- 2025: 1 · 2024: 1 · 2023: 5 · 2022: 3 · 2021: 5 · 2020: 2 · 2019: 4 · 2018: 4 · 2017: 4 · 2016: 5 · 2015: 4 · 2014: 7 · 2013: 6 · 2012: 17
- FWCI
- 36.80
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference (publishedVersion)
- TU/e Research Portal (submittedVersion)
- TNO Repository (submittedVersion)
- Repository hosted by TU Delft Library (TU Delft) (submittedVersion)
- Data Archiving and Networked Services (DANS) (submittedVersion)
- Topics
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
- Keywords
- successive approximation register ADC, low-power analog-to-digital converter, 90 nm CMOS, energy efficiency, 8-bit ADC
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