A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS
Open accessAbstract
During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology. The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers. At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 µW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is reduced to only 0.26 µW. The occupied area of the implemented ADC is 0.074 mm 2 .
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Written from the paper’s full text.
TL;DR
This paper presents a 10-bit differential asynchronous SAR ADC in 65-nm CMOS designed for low-power, flexible-rate operation from 0.01 to 12 MS/s. Post-layout simulations show nearly constant ENOB around 9.6 while power scales from 0.26 µW at 10 kS/s to 151.4 µW at 12 MS/s.
Key findings
- At 12.0 MS/s, the ADC achieved ENOB 9.65, SNDR 59.8 dB, power 151.4 µW, and FoM 15.8 fJ/Conversion-step; at 10.0 kS/s, ENOB was 9.63 with power reduced to 0.26 µW. Occupied area was 0.074 mm².
- Typical-corner post-layout simulation gave worst DNL 0.52 LSB and INL 0.53 LSB, with gain error 18.1 LSB (<1.8% FS) and offset error −11.1 LSB (<1.1% FS).
- DAC capacitor mismatch Monte Carlo showed DNL mean 0 and standard deviation 0.098 LSB, and ENOB mean 9.94 with standard deviation 0.047.
- Under PVT worst cases at 12.0 MS/s, the circuit showed ENOB 9.44 (@FF, 1.32 V, 0 °C), power 228 µW (@FF, 1.32 V, 85 °C), and CER 4.95×10⁻⁹ (@SS, 1.08 V, 85 °C); typical CER was below 10⁻²⁵⁸ error/sample.
Methods
- The work designed and simulated a differential asynchronous SAR ADC in 65-nm CMOS using a split binary-weighted capacitive DAC with merged capacitor switching, bootstrapped input switches, a low-kickback dynamic comparator, and custom asynchronous SAR logic.
- Static DNL/INL were extracted by code density analysis from a transient simulation converting 10,240 samples of a differential ramp input; dynamic ENOB and power were extracted from transient simulations converting 1024 samples of a differential sinusoid near Nyquist, with 90% input range and 0.6 V common mode, using coherent sampling.
- Metastability and CER were estimated from comparator transient simulations with geometrically spaced input voltages to extract the regeneration time constant τ = 29 ps, then evaluated across process, supply, and temperature corners.
Limitations
- The paper states that some digital circuitry was implemented with foundry standard cells, so better power consumption could be achieved using only custom cells; it also states that CER is the most PVT-sensitive parameter, with the exponent varying from −601 in the typical case to −26.7 in the worst tested condition, causing CER to range from 10⁻²⁵⁸ to 10⁻⁹, and that limiting supply to VDD ±5% greatly reduces CER.
- Evident from the text: all reported ADC performance results are post-layout simulation results, not measured silicon results; Table 3 explicitly labels this work as “*Post-layout simulation results” while the compared works are marked as measurement typical results. No fabricated-chip measurement validation is reported.
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Claims the paper makes
0 of 23 cited sources checked · 0 supported · 0 flagged
- Findingown data
The implemented ADC occupies an area of 0.074 mm2.
“The occupied area of the implemented ADC is 0.074 mm 2 .”
Quote in the paperNot a substantial claim - Findingown data
The designed differential asynchronous SAR ADC in 65-nm CMOS operates over a flexible sampling-rate range from a few kS/s up to 12.0 MS/s.
“The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers.”
- Also stated in: § 1 Introduction · plain
“This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology, with a flexible sampling rate ranging from a few kS/s up to 12 MS/s.”
Quote in the paperSubstantial claim - Also stated in: § 1 Introduction · plain
- Findingown data
Most of the ADC current consumption occurs in the interval between the rising of the sampling clock and the rising of the eoc flag.
“Most of the ADC current consumption is observed to occur in the interval between the rising of the sampling clock signal (triggering of the asynchronous logic circuit) and the rising of the eoc flag.”
Quote in the paperSubstantial claim - Findingown data
At 10.0 kS/s sampling rate, the ENOB is 9.63.
“In post-layout simulations, at maximum sampling rate of 12.0 MS/s, the circuit achieved an ENOB of 9.65 and a power consumption of 151.4 lW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is cut to only 0.26 lW.”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
At 10.0 kS/s sampling rate, the power consumption is 0.26 uW.
“In post-layout simulations, at maximum sampling rate of 12.0 MS/s, the circuit achieved an ENOB of 9.65 and a power consumption of 151.4 lW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is cut to only 0.26 lW.”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
In post-layout simulations, at maximum sampling rate of 12.0 MS/s, the circuit achieved an ENOB of 9.65.
“In post-layout simulations, at maximum sampling rate of 12.0 MS/s, the circuit achieved an ENOB of 9.65 and a power consumption of 151.4 lW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is cut to only 0.26 lW.”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
For typical corner model and VDD = 1.2 V, the worst INL error was 0.53 LSB.
“For typical corner model and V DD = 1.2 V, the worst DNL and INL errors were found to be, respectively, 0.52 LSB and 0.53 LSB.”
Quote in the paperNot a substantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
With these parameters, P_meta has an extremely small value, on the order of 10^-258 error/sample.
“With these parameters, we find that P meta has an extremely small value, on the order of 10 -258 error/sample, leading to an irrelevant CER.”
Quote in the paperNot a substantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
The coefficient 'Power/Sampling frequency' is roughly constant for sampling rates ranging from 0.1 up to 12.0 MS/s.
“By drawing the Fig. 15, the coefficient ''Power/Sampling frequency'' is observed to be roughly constant for sampling rates ranging from 0.1 up to 12.0 MS/s.”
Quote in the paperNot a substantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
In the worst PVT condition when supply is limited to VDD ± 5%, the CER is as low as 1.92e-59 (@SS, 1.14 V, 85 °C).
“In such circumstance, the worst PVT condition is (@SS, 1.14 V, 85 8C) with a CER as low as 1.92Á10 -59 .”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
For typical corner model and VDD = 1.2 V, post-layout simulations of the comparator show that s = 29 ps.
“For typical corner model and V DD = 1.2 V, post-layout simulations of the comparator show that s = 29 ps and the simulations of the ADC at 12.0 MS/s show that t margin- = (T St track -T FIX,TOT -T easy ) are close to 17.4 ns.”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
The simulated power consumption of the circuit presented an almost linear dependency on the sampling frequency.
“As expected, the simulated power consumption of the circuit presented an almost linear dependency of the sampling frequency.”
Quote in the paperNot a substantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
For typical corner model and VDD = 1.2 V, simulations of the ADC at 12.0 MS/s show that t_margin is close to 17.4 ns.
“For typical corner model and V DD = 1.2 V, post-layout simulations of the comparator show that s = 29 ps and the simulations of the ADC at 12.0 MS/s show that t margin- = (T St track -T FIX,TOT -T easy ) are close to 17.4 ns.”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
In the worst cases of PVT variations, at 12.0 MS/s, the circuit presented a CER of 4.95e-9 (@SS, 1.08 V, 85 °C).
“In the worst cases of PVT variations, at 12.0 MS/s, the circuit presented a 9.44 ENOB (@FF, 1.32 V, 0 °C), a power consumption of 228 lW (@FF, 1.32 V, 85 °C) and a CER of 4.95Á10 -9 (@SS, 1.08 V, 85 °C).”
Quote in the paperNot a substantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
For typical corner model and VDD = 1.2 V, the worst DNL error was 0.52 LSB.
“For typical corner model and V DD = 1.2 V, the worst DNL and INL errors were found to be, respectively, 0.52 LSB and 0.53 LSB.”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
The calculated gain error is 18.1 LSB (less than 1.8% of the full-scale range).
“The calculated gain error is 18.1 LSB (less than 1.8% of the full-scale range) whereas the calculated offset error is -11.1 LSB (less than 1.1% of the full-scale range).”
Quote in the paperNot a substantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
In the worst cases of PVT variations, at 12.0 MS/s, the circuit presented a power consumption of 228 uW (@FF, 1.32 V, 85 °C).
“In the worst cases of PVT variations, at 12.0 MS/s, the circuit presented a 9.44 ENOB (@FF, 1.32 V, 0 °C), a power consumption of 228 lW (@FF, 1.32 V, 85 °C) and a CER of 4.95Á10 -9 (@SS, 1.08 V, 85 °C).”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
In post-layout simulations, at maximum sampling rate of 12.0 MS/s, the circuit achieved a Figure of Merit of 15.8 fJ/Conversion-step.
“In post-layout simulations, at maximum sampling rate of 12.0 MS/s, the circuit achieved an ENOB of 9.65 and a power consumption of 151.4 lW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is cut to only 0.26 lW.”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
In post-layout simulations, at maximum sampling rate of 12.0 MS/s, the circuit achieved a power consumption of 151.4 uW.
“In post-layout simulations, at maximum sampling rate of 12.0 MS/s, the circuit achieved an ENOB of 9.65 and a power consumption of 151.4 lW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is cut to only 0.26 lW.”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
In the worst cases of PVT variations, at 12.0 MS/s, the circuit presented a 9.44 ENOB (@FF, 1.32 V, 0 °C).
“In the worst cases of PVT variations, at 12.0 MS/s, the circuit presented a 9.44 ENOB (@FF, 1.32 V, 0 °C), a power consumption of 228 lW (@FF, 1.32 V, 85 °C) and a CER of 4.95Á10 -9 (@SS, 1.08 V, 85 °C).”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Findingown data
The calculated offset error is -11.1 LSB (less than 1.1% of the full-scale range).
“The calculated gain error is 18.1 LSB (less than 1.8% of the full-scale range) whereas the calculated offset error is -11.1 LSB (less than 1.1% of the full-scale range).”
Quote in the paperNot a substantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Interpretationcitation
Because the conversion interval and the operations performed in it do not scale with sampling frequency, power consumption is expected to have an almost linear relation with sampling frequency.
“Since the size of this time interval and the amount of operations performed in it do not scale with the sampling frequency, it is expected an almost linear relation between power consumption and sampling frequency [8].”
Quote in the paperNot a substantial claim0 of 1 sources checked- cites [8] Harpe, P., Zhou, C., Wang, X., Dolmans, G., & de Groot, H. (2010). A 30fJ/Conversion-Step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm. In: 2010 IEEE International Solid-State Circuits Conference (ISSCC), Feb (pp. 388–389). source
- Interpretationreasoning
The designed ADC can be employed in the frontend of IEEE 802.15.4 standard receivers, such as Zigbee and Thread, for bandwidths from 200 kHz to 5.0 MHz.
“The designed ADC can also be employed in the frontend of IEEE 802.15.4 standard receivers, like Zigbee and Thread, working in bandwidths ranging from 200 kHz up to 5.0 MHz.”
Quote in the paperNot a substantial claim - Interpretationreasoning
The almost linear power-sampling frequency relation is compromised at very low sampling frequencies because ADC power consumption is dominated by static power consumption.
“This relation is compromised for very low sampling frequencies, once in this case the ADC power consumption is dominated by the static power consumption.”
Quote in the paperNot a substantial claim- Rests on an assumption: At very low sampling frequencies, ADC power consumption is dominated by static power consumption.
- Interpretationreasoning
Because VTH depends on vin, charge injection results in different charges redistributed to each side of the differential input.
“Unfortunately, V TH depends on vin, which will result in different charges redistributed to each side of the differential input.”
Quote in the paperSubstantial claim - Interpretationnone given
All the modifications resulted in an ADC with a performance comparable with the best circuits of the literature.
“All the modifications resulted in an ADC with a performance comparable with the best circuits of the literature.”
Quote in the paperNot a substantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Premisecitation
A split binary-weighted capacitive array structure reduces the required number of unitary capacitors in the DAC.
“A split binary-weighted capacitive array structure [11] was applied in this design to considerably reduce the required number of unitary capacitors in the DAC.”
Quote in the paperSubstantial claim0 of 1 sources checked- cites [11] Baker, R. J. (2010). CMOS circuit design, layout and simulation. New Jersey: Willey-IEEE Press. source
- Interpretationreasoning
In the comparator topology, opening M3 and M4 during the final part of regeneration and most of the reset reduces the M1/M2 gate-drain voltage swing, thereby reducing kickback noise coupling between ap2/an2 and vinp/vinn.
“Once the drain terminals of the differential pair will not sense the voltage swing driven by the cross-coupled pairs, this topology will reduce the M 1 and M 2 gate-drain voltage swing, therefore, reducing noise coupling between ap2/an2 and vinp/vinn through the gate-drain capacitances C GD of M 1 and M 2 (kickback noise).”
Quote in the paperSubstantial claim - Premisecitation
The chosen Cu value also meets the requirement that thermal noise introduced by the switches must be smaller than the quantization noise of an ideal 10-bit ADC.
“This value also meets with the requirement that the thermal noise introduced by the switches must be smaller than the quantization noise of the ideal 10-bit ADC [2].”
Quote in the paperSubstantial claim0 of 1 sources checked- cites [2] de Plassche, R. J. V. (2003). CMOS integrated analog-to-digital and digital-to-analog converters. Dordrecht: KAP. source
- Interpretationown data
For more strict applications, the CER of the ADC can be greatly reduced by limiting the supply voltage to VDD ± 5%.
“For more strict applications, the CER of the ADC can be greatly reduced by limiting the supply voltage to V DD ± 5%.”
Quote in the paperNot a substantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Premisecitation
Asynchronous time allocation reduces the data Code Error Rate compared with a synchronous counterpart of the same resolution, due to an exponential reduction in the probability of a metastability event.
“As shown in [10], this feature reduces the data Code Error Rate of the converter, CER, due to the exponential reduction, when compared with its synchronous counterpart of same resolution, in the probability of a metastability event occurring in the conversion of a sample, P meta .”
Quote in the paperSubstantial claim0 of 1 sources checked- cites [10] Yu, A., Bankman, D., Zheng, K., & Murmann, B. (2019). Understanding metastability in SAR ADCs: part II: asynchronous. IEEE Solid-State Circuits Magazine, 11(3), 16–32. source
- Interpretationown data
The performance degradation caused by the chosen Cu value is small.
“These results show that the performance degradation caused by the chosen C u value is small.”
Quote in the paperSubstantial claim - Premisecitation
Bootstrapped switches provide low-distortion differential sampling by keeping the gate-to-source voltage of the effective switch transistor nearly constant.
“To provide a low distortion differential sampling, bootstrapped switches [9] were considered in the design.These switches keeps the gate to source voltage of an effective switch transistor nearly constant.”
Quote in the paperSubstantial claim0 of 1 sources checked- cites [9] Abo, A. M., & Gray, P. R. (1999). A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE Journal of Solid-State Circuits, 34(5), 599–606. source
- Premisecitation
In typical split capacitive array implementations, an additional unitary capacitor Cf in parallel with the sub DAC capacitors is necessary to provide correct binary weighted steps in the switching.
“In typical implementations of the split capacitive array structure, there is an additional unitary capacitor C f in parallel with the capacitors of the sub DAC.This capacitor C f has one of its plates permanently connected to V CM , and it is necessary to provide correct binary weighted steps in the switching.”
Quote in the paperNot a substantial claim0 of 1 sources checked- cites [11] Baker, R. J. (2010). CMOS circuit design, layout and simulation. New Jersey: Willey-IEEE Press. source
- Interpretationown data
The ADC is suitable for a wide spectrum of low power applications.
“The table shows that the ADC can operate with sampling rate ranging from 10 kS/s up to 12 MS/s with practically constant ENOB and reduced power consumption, confirming that the ADC is suitable for a wide spectrum of low power applications.”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Premisecitation
For a differential array to provide 3-sigma yield, the minimum value for Cu is given by Eq. (1).
“For a differential array to provide 3-sigma yield, the minimum value for C u is given by [13]”
Quote in the paperSubstantial claim0 of 1 sources checked- cites [13] Zhang, D. (2012). Design of Ultra-Low-Power Analog-to-Digital Converters, Ph.D thesis, The Institute of Technology at Linköping University, Linköping.
- Interpretationown data
The CER due to metastability is irrelevant.
“With these parameters, we find that P meta has an extremely small value, on the order of 10 -258 error/sample, leading to an irrelevant CER.”
Quote in the paperNot a substantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Premisecitation
An exaggerated comparator offset could decrease SNR by reducing the input voltage swing.
“Still, an exaggerated offset could decrease the signalto-noise ratio (SNR) by reducing the input voltage swing [13].”
Quote in the paperNot a substantial claim0 of 1 sources checked- cites [13] Zhang, D. (2012). Design of Ultra-Low-Power Analog-to-Digital Converters, Ph.D thesis, The Institute of Technology at Linköping University, Linköping.
- Interpretationcitation
The obtained CERs are compatible with the necessary Bit Error Rate (BER) reported in the literature for low power Zigbee and BLE frontends, ranging from 10^-6 up to 10^-3.
“Even so, the obtained CERs are compatible with the necessary Bit Error Rate (BER) reported in the literature for low power Zigbee and BLE frontends [19,20], ranging from 10 -6 up to 10 -3 .”
Quote in the paperSubstantial claim0 of 2 sources checked- cites [19] Pereira, M. S., Vaz, J. C., Leme, C. A., de Sousa, J. T., & Freire, J. C. (2015). An ultra-low power low-IF GFSK demodulator for Bluetooth-LE applications. In: 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May (pp. 1226–1229). source
- cites [20] Pengg, F., Barras, D., Kucera, M., Scolari, N., & Vouilloz, A. (2013). A low power miniaturized 1.95mm2 fully integrated transceiver with fastPLL mode for IEEE 802.15.4/bluetooth smart and proprietary 2.4GHz applications. In: 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June (pp. 71–74). source
- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Premisecitation
For a split capacitive array with L = 4, the bridge capacitor should ideally present a capacitance of (16/15)Cu.
“In this case, the bridge capacitor (C bridge ) should ideally present a capacitance of (16/15)ÁC u , [11] when L = 4.”
Quote in the paperNot a substantial claim0 of 1 sources checked- cites [11] Baker, R. J. (2010). CMOS circuit design, layout and simulation. New Jersey: Willey-IEEE Press. source
- Premisecitation
In asynchronous SAR ADCs, the available conversion time is allocated to each comparison according to its difficulty, so more time can be used for harder comparisons.
“In consequence, more time can be employed in the harder comparisons.”
Quote in the paperSubstantial claim0 of 1 sources checked- cites [10] Yu, A., Bankman, D., Zheng, K., & Murmann, B. (2019). Understanding metastability in SAR ADCs: part II: asynchronous. IEEE Solid-State Circuits Magazine, 11(3), 16–32. source
- Interpretationreasoning
Once the sampling period TS is chosen, reducing the comparator regeneration time constant sigma is the best way to keep Pmeta and CER low.
“Once the value of T S was chosen, the best way to keep P meta and CER low is through the reduction of s.”
Quote in the paperSubstantial claim - Premisecitation
The maximum allowed switch resistance for charging the DAC capacitors within half the sampling period with a maximum error of VLSB is constrained by Eq. (4).
“Therefore, the maximum allowed switch resistance for charging the DAC capacitors within half the sampling period with a maximum error of V LSB , as analyzed in [13], is constrained by”
Quote in the paperSubstantial claim0 of 1 sources checked- cites [13] Zhang, D. (2012). Design of Ultra-Low-Power Analog-to-Digital Converters, Ph.D thesis, The Institute of Technology at Linköping University, Linköping.
- Premisenone given
In the implemented DAC without Cf, the bridge capacitor should present a value close to 1.0669 Cu.
“In the implementation of Fig. 4, the capacitor C f is not present.In this case, the bridge capacitor should present a value close to (1.0669)ÁC u .”
Quote in the paperNot a substantial claim - Interpretationown data
The CER presented itself as the most sensitive parameter because the exponent of Eq. (5), t_margin/s, varies significantly for different PVT conditions.
“The CER presented itself as the most sensitive parameter because the exponent of Eq. ( 5),t margin /s, varies significantly for different PVT conditions.”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- Interpretationown data
The implemented ADC can be employed in a wide range of low power, moderate resolution systems.
“These results show that the implemented ADC can be employed in a wide range of low power, moderate resolution systems as expected.”
Quote in the paperNot a substantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
- May combine two claims. 26
- Classified as probably not a substantial claim. 1
May combine two claims.
Findingown dataAt 10.0 kS/s sampling rate, the ADC achieved an ENOB of 9.63 and a power consumption of 0.26 lW.
“at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is reduced to only 0.26 lW.”
Quote in the paperSubstantial claimMay combine two claims.
Findingown dataAt maximum sampling rate, the post-layout simulated ADC achieved an ENOB of 9.65 and a power consumption of 151.4 lW, yielding a Figure of Merit of 15.8 fJ/conversion-step.
“At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 lW, leading to a Figure of Merit of 15.8 fJ/Conversion-step;”
Quote in the paperSubstantial claimMay combine two claims.
FindingcitationThe applied merged capacitor switching scheme reduced the current sink from vrefp and kept low the power consumption wasted with the DAC charge distribution.
“Additionally, the applied merged capacitor switching scheme [12] reduced the current sink from vrefp and kept low the power consumption wasted with the DAC charge distribution.”
Quote in the paperSubstantial claim0 of 1 sources checked- cites [12] Hariprasath, V., Guerber, J., Lee, S.-H., & Moon, U.-K. (2010). Merged capacitor switching based SAR ADC with highest switching energy-efficiency. Electronics Letters, 46(9), 620–621. source
- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
May combine two claims.
Findingown dataCapacitor mismatches influence ENOB, which has mean 9.94 and standard deviation 0.047.
“The capacitor mismatches also influence the effective number of bits, ENOB, which will have mean of 9.94 and standard deviation of 0.047.”
Quote in the paperSubstantial claimMay combine two claims.
Findingown dataThe biggest contributions to the power consumption are given by the digital circuitry (current sinking from vddd) and by the capacitive DAC (current sinking from vrefp).
“The biggest contributions to the power consumption are given by the digital circuitry (current sinking from vddd) and by the capacitive DAC (current sinking from vrefp).”
Quote in the paperNot a substantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
May combine two claims.
Findingown dataThe exponent t_margin/s can change from -601 in the typical case to -26.7, the highest value obtained among all tested conditions.
“Notice that the exponent can change from -601, in the typical case, to -26.7, the highest valor obtained among all tested conditions.”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
May combine two claims.
Findingown dataDNL errors caused only by DAC capacitor mismatches have mean zero and standard deviation 0.098 LSB.
“The DNL errors mean and standard deviation are zero and 0.098 LSB, respectively.”
Quote in the paperSubstantial claimMay combine two claims.
PremisecitationAsynchronous SAR ADCs require only one clock signal to control sampling, which relaxes clock distribution requirements.
“On the other hand, asynchronous SAR ADCs [7,8] require only one clock signal to control the sampling.This feature relaxes the clock distribution requirements.”
Quote in the paperSubstantial claim0 of 2 sources checked- cites [7] Chen, S.-W.M., & Brodersen, R. W. (2006). A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-µm CMOS. IEEE Journal of Solid-State Circuits, 41(12), 2669–3680. source
- cites [8] Harpe, P., Zhou, C., Wang, X., Dolmans, G., & de Groot, H. (2010). A 30fJ/Conversion-Step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm. In: 2010 IEEE International Solid-State Circuits Conference (ISSCC), Feb (pp. 388–389). source
May combine two claims.
PremisecitationThe designed ADC has a differential architecture to minimize common-mode noise effects and reduce even-order harmonic distortion.
“Additionally, the designed ADC has a differential architecture to minimize the effects of common-mode noise and to reduce the even order harmonics distortion [2].”
Quote in the paperNot a substantial claim0 of 1 sources checked- cites [2] de Plassche, R. J. V. (2003). CMOS integrated analog-to-digital and digital-to-analog converters. Dordrecht: KAP. source
May combine two claims.
InterpretationreasoningThe proposed ADC can handle from a single neural signal, with power consumption lower than 1.0 lW, up to almost 500 diverse neural signals.
“The proposed ADC can handle from a single neural signal, with power consumption lower than 1.0 lW, up to almost 500 diverse neural signals.”
Quote in the paperSubstantial claim- Rests on an assumption: A single neuronal signal requires an ADC with no more than 20 kS/s, at least 10 bits, and minimum power consumption to avoid damaging living cells and extend battery life.
May combine two claims.
PremisecitationThe SAR architecture has few analog blocks, only switches and one comparator, and a simple design, making it well suited for moderate-resolution and low-to-medium data-rate applications.
“The SAR architecture, which presents few analog blocks (only switches and one comparator) and a simple design, is well suited for moderate resolution and low-to-medium data rate applications [3].”
Quote in the paperNot a substantial claim0 of 1 sources checked- cites [3] Fredenburg, J., & Flynn, M. P. (2015). ADC trends and impact on SAR architecture and analysis. In: 2015 IEEE Custom Integrated Circuits Conference (CICC), Sept (pp. 1–8). source
May combine two claims.
Premisenone givenSetting M and L, the numbers of switches in the main and sub DACs, to 5 and 4 leads to the minimal number of unitary capacitors needed to implement the arrays, improving matching and connection routing.
“M and L, the number of switches in the main and in the sub DAC, were set to 5 and 4, respectively, because this choice leads to the minimal number of unitary capacitors needed to implement the arrays, improving the matching and connection routing between these devices.”
Quote in the paperSubstantial claimMay combine two claims.
Study design and conductreasoningErrors due to charge injection should not be greater than VLSB, constraining the maximum allowed W11 by Eq. (3).
“The errors due to charge injection should not be greater than V LSB = V FS /2 N , and the maximum allowed W 11 is constrained by”
Quote in the paperSubstantial claimMay combine two claims.
PremisecitationLatch offset, when the common-mode voltage is kept constant, is not affected by input values, is almost time invariant, and slightly influences ADC linearity.
“In fact, the latch offset, when the common-mode voltage is kept constant, is not affected by the input values and, in consequence, is almost time invariant and slightly influence the ADC linearity [16].”
Quote in the paperNot a substantial claim0 of 1 sources checked- cites [16] Liu, C.-C., Chang, S.-J., Huang, G.-Y., & Lin, Y.-Z. (2010). A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE Journal of Solid-State Circuits, 45(4), 731–740. source
May combine two claims.
Study design and conductreasoningThe utilization of the delayed version of next_bit_set, bit_set_dly, provides a longer time for the preparation of the node bit and ensures that this signal is stable when s0_n is set to high, avoiding glitches in the NAND gates.
“The utilization of the delayed version of next_bit_set, bit_set_dly, will provide a longer time for the preparation of the node bit and ensure that this signal is stable when s0_n is set to high.This will avoid glitches in the NAND gates.”
Quote in the paperSubstantial claimProbably not a substantial claim: may not pass S3 (load-bearing).
InterpretationreasoningBetter power consumption could be achieved if only custom cells were employed instead of foundry standard digital library cells.
“Some of the digital circuitry was implemented with cells from the foundry standard digital library, which means that better power consumption could be achieved if only custom cells were employed.”
Quote in the paperNot a substantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
May combine two claims.
Premisenone givenParasitic capacitances at nodes vdac_n/vdac_p and vdac_nx/vdac_px introduce additional offset and gain errors; if those capacitances are Cp and Cpx, the offset error is around (16Cp - Cpx)/Cu LSB.
“In addition to the errors caused by the bridge capacitor value, parasitic capacitances between nodes vdac_n, vdac_p, vdac_nx, and vdac_px and V DD or ground will introduce an additional offset and gain errors.If the parasitic capacitances in the nodes vdac_n/vdac_p are C p and in the nodes vdac_nx/vdac_px are C px , the offset error is around (16ÁC p ? C px )/C u LSB.”
Quote in the paperSubstantial claimMay combine two claims.
Study design and conductnone givenDue to the careful design of the DAC Switch Control logic, the nodes s0, s1, and s2 are never set to high at the same time, avoiding temporary short circuits between VCM and VREFN or VREFP power sources.
“Note that, due to the careful design of the DAC Switch Control logic, the nodes s0, s1, and s2 are never set to high at the same time, avoiding temporary short circuits between V CM and V REFN or V REFP power sources.”
Quote in the paperNot a substantial claimMay combine two claims.
PremisecitationA custom combinational asynchronous SAR logic based on the circuit described in [8], with modifications to support the merged capacitor switching scheme, allows manual device placement, presents reduced power consumption, and uses only one clock source.
“In this work, a custom combinational asynchronous SAR logic, based on the circuit described in [8], with modifications to support the merged capacitor switching scheme was employed.This asynchronous logic allows a ''manual'' device placement, presents reduced power consumption and makes use of only one clock source.”
Quote in the paperSubstantial claim0 of 1 sources checked- cites [8] Harpe, P., Zhou, C., Wang, X., Dolmans, G., & de Groot, H. (2010). A 30fJ/Conversion-Step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm. In: 2010 IEEE International Solid-State Circuits Conference (ISSCC), Feb (pp. 388–389). source
May combine two claims.
PremisecitationThe dynamic comparator topology of [15] has a low regeneration time constant and reduced kickback noise.
“The dynamic comparator topology of [15] was considered in this work since it presents a low regeneration time constant and, as an additional advantage, a reduced kickback noise.”
Quote in the paperSubstantial claim0 of 1 sources checked- cites [15] Huang, Y., Schleifer, H., & Killat, D. (2013). Design and Analysis of Novel Dynamic Latched Comparator with Reduced Kickback Noise for High-speed ADCs. In: 2013 European Conference on Circuit Theory and Design (ECCTD), Sept (pp. 1–4). source
May combine two claims.
InterpretationreasoningIn the bootstrapped circuit, (VG - vin) = VDD, so at first analysis charge injection would affect vdac_p and vdac_n evenly and would not affect ADC evaluation.
“In the bootstrapped circuit, (V Gvin) = V DD and, at first analysis, the charge injection would affect vdac_p and vdac_n evenly.In this case, the ADC evaluation would not be affected by the charge injection.”
Quote in the paperSubstantial claimMay combine two claims.
Interpretationown dataThe ADC can operate with sampling rate ranging from 10 kS/s up to 12 MS/s with practically constant ENOB and reduced power consumption.
“The table shows that the ADC can operate with sampling rate ranging from 10 kS/s up to 12 MS/s with practically constant ENOB and reduced power consumption, confirming that the ADC is suitable for a wide spectrum of low power applications.”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
May combine two claims.
PremisecitationImplementing the bridge capacitor as a unitary capacitor introduces a -1.0 LSB offset and a tolerably small gain error in the DAC transfer curve.
“When the bridge capacitor is implemented as a unitary capacitor, a common practice as mentioned, a -1.0 LSB (Least Significant Bit) offset and a tolerably small gain error are introduced in the DAC transfer curve [13].”
Quote in the paperNot a substantial claim0 of 1 sources checked- cites [13] Zhang, D. (2012). Design of Ultra-Low-Power Analog-to-Digital Converters, Ph.D thesis, The Institute of Technology at Linköping University, Linköping.
May combine two claims.
PremisereasoningThe DAC implementation without Cf and with Cbridge = Cu causes only offset and small gain errors, but not alteration in the code length of the transfer curve.
“Since the offset errors due to the parasitic capacitors are probably higher than 1.0 LSB and the DAC implementation without C f and with C bridge = C u causes only offset and small gain errors, but not alteration in the code length of the transfer curve, such implementation was chosen for application in the ADC.”
Quote in the paperSubstantial claim- Rests on an assumption: Offset errors due to parasitic capacitors are probably higher than 1.0 LSB.
May combine two claims.
PremisecitationThe merged capacitor switching scheme provides good switching efficiency and low digital circuitry complexity.
“It provides good switching efficiency and a low digital circuitry complexity.”
Quote in the paperSubstantial claim0 of 1 sources checked- cites [12] Hariprasath, V., Guerber, J., Lee, S.-H., & Moon, U.-K. (2010). Merged capacitor switching based SAR ADC with highest switching energy-efficiency. Electronics Letters, 46(9), 620–621. source
May combine two claims.
InterpretationreasoningThe wide variation in the exponent causes a huge variation in the CER value, which goes from 10^-258 to 10^-9.
“This wide variation in the exponent will cause, in turn, a huge variation in the CER value, which goes from 10 -258 to 10 -9 .”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
May combine two claims.
Interpretationown dataA low power, differential, asynchronous 10-bit SAR ADC was successfully designed, drawn to layout and simulated.
“A low power, differential, asynchronous 10-bit SAR ADC was successfully designed, drawn to layout and simulated.”
Quote in the paperSubstantial claim- Rests on an assumption: Post-layout simulations accurately predict the performance of the fabricated ADC.
The paper relies on this without support.
A single neuronal signal requires an ADC with no more than 20 kS/s, at least 10 bits, and minimum power consumption to avoid damaging living cells and extend battery life.
“A single neuronal signal needs, for its capture, an ADC with no more than 20 kS/s, at least 10 bits, and minimum power consumption in order to not damage the living cells and extend batteries life.”
The paper relies on this without support.
Offset errors due to parasitic capacitors are probably higher than 1.0 LSB.
“Since the offset errors due to the parasitic capacitors are probably higher than 1.0 LSB”
The paper relies on this without support.
At very low sampling frequencies, ADC power consumption is dominated by static power consumption.
“This relation is compromised for very low sampling frequencies, once in this case the ADC power consumption is dominated by the static power consumption.”
The paper relies on this without support.
The symmetry in the layout of a differential ADC can affect the system linearity.
“The symmetry in the layout of a differential ADC can affect the system linearity.”
The paper relies on this without support.
Any asymmetry in the comparator implementation directly affects its offset voltage.
“Although the comparator presents itself as a single circuit, any asymmetry in its implementation directly affects its offset voltage.”
The paper relies on this without support.
For the least significant bits, the delay of the logic circuits is enough to ensure the small amount of charge is properly redistributed before the next comparison.
“For the least significant bits, however, delay cells were not necessary because the delay of the logic circuits is enough to ensure the small amount of charge is properly redistributed before the next comparison.”
The paper relies on this without support.
Post-layout simulations accurately predict the performance of the fabricated ADC.
“The performance of the ADC was verified by running postlayout simulations with Cadence Spectre simulator.”
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Liu, C.-C., Chang, S.-J., Huang, G.-Y., & Lin, Y.-Z. (2010) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2010.2042254 · Cited by 1,329 · see citing works
A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
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A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu{\hbox{m}}$ CMOS
Chen, S.-W. M., & Brodersen, R. W. (2006) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2006.884231 · Cited by 423 · see citing works
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Plassche, R. (2003) · doi:10.1007/978-1-4757-3768-4 · Cited by 394 · see citing works
Merged capacitor switching based SAR ADC with highest switching energy-efficiency
Hariprasath, V., Guerber, J., Lee, S.-H., & Moon, U.-K. (2010) · Electronics Letters · doi:10.1049/el.2010.0706 · Cited by 298 · see citing works
A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC
van Elzakker, M., van Tuijl, E., Geraedts, P. F. J., et al. (2008) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.2008.4523148 · Cited by 189 · see citing works
A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS
Chen, S.-W. M., & Brodersen, R. W. (2006) · Cited by 137 · see citing works
A 10-b 50-MS/s 820-$\mu $W SAR ADC With On-Chip Digital Calibration
Yoshioka, M., Ishikawa, K., Takayama, T., et al. (2010) · IEEE Transactions on Biomedical Circuits and Systems · doi:10.1109/tbcas.2010.2081362 · Cited by 129 · see citing works
A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS
Harpe, P., Zhou, C., Wang, X., Dolmans, G., & de Groot, H. (2010) · 2010 IEEE International Solid-State Circuits Conference - (ISSCC) · doi:10.1109/isscc.2010.5433967 · Cited by 96 · see citing works
A 1V 11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18µm CMOS
Liu, C.-C., Chang, S.-J., Huang, G., et al. (2010) · Symposium on VLSI Circuits · doi:10.1109/vlsic.2010.5560283 · Cited by 91 · see citing works
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC
Kim, W., Hong, H.-K., Roh, Y.-J., et al. (2016) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2016.2563780 · Cited by 81 · see citing works
A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC
Zhijie, C. H. E. N., Miyahara, M., & Matsuzawa, A. (2016) · IEICE Transactions on Electronics · doi:10.1587/transele.e99.c.963 · Cited by 62 · see citing works
Design and characterization of low-voltage analog switch without the need for clock boosting
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Understanding Metastability in SAR ADCs: Part II: Asynchronous
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Huang, Y., Schleifer, H., & Killat, D. (2013) · 2013 European Conference on Circuit Theory and Design (ECCTD) · doi:10.1109/ecctd.2013.6662236 · Cited by 20 · see citing works
ADC trends and impact on SAR ADC architecture and analysis
Fredenburg, J., & Flynn, M. P. (2015) · 2015 IEEE Custom Integrated Circuits Conference (CICC) · doi:10.1109/cicc.2015.7338380 · Cited by 18 · see citing works
Ultra Low-Power Integrated Circuit Design for Wireless Neural Interfaces
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Understanding Metastability in SAR ADCs: Part I: Synchronous
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An ultra-low power low-IF GFSK demodulator for Bluetooth-LE applications
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Design of a low power 10-bit 12MS/s asynchronous SAR ADC in 65nm CMOS
Campos, A. L., Navarro, J., & Luppe, M. (2019) · Symposium on Integrated Circuits and Systems Design · doi:10.1145/3338852.3339857 · Cited by 3 · see citing works
Self-citationBit-error rate measurement setup and comparator design
Agah, A. (2009) · Research Repository (Delft University of Technology) · Cited by 2 · see citing works
A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC
Chen, Z., Miyahara, M., & Matsuzawa, A. (2015) · 2015 Symposium on VLSI Circuits (VLSI Circuits) · doi:10.1109/vlsic.2015.7231329
A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter
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Flagged first, then by citations
Cited by
Sorted by citations
A 13.8pJ/conv-step binary search ADC with reusable comparator architecture
Dipti, Singh, S. V., Kumawat, T., et al. (2021) · AEU - International Journal of Electronics and Communications · doi:10.1016/j.aeue.2021.154056 · Cited by 9 · see citing works
A 1.2-V 7.76-ENOB 1-MS/s single-ended SAR ADC in 65-nm CMOS for biomedical applications
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A 0.7-V 9-bit 2-MS/s SAR ADC with a novel energy-efficient switching methodology in 40-nm CMOS
Huang, L., & Wu, J. (2024) · IEEE International Conference on Electronic Technology, Communication and Information (ICETCI) · doi:10.1109/icetci61221.2024.10594216
“The proposed SAR ADC attains a FOM W of 2.61 fJ/conversion-step, rivaling the performance of previous studies reported in [6-8].”
ResultInfluentialDesign of a low-distortion bootstrapped switch for non-uniform sampling of biomedical signals
Nasrabadi, S. B., Dolatshahi, M., Zanjani, S. M., et al. (2025) · Analog Integrated Circuits and Signal Processing · doi:10.1007/s10470-025-02384-2
“Uniform sampling is performed at a single sampling frequency [17–20], while in the biosignal processing circuits, the reduction in the sampled data length and as a result the low power consumption of the circuit are important design issues.”
A 0.5 V 10-bit 500 KS/s SAR ADC with Energy-Efficiency Switching Scheme and Low-Noise Comparator
Cui, X., Dong, D., Li, Z., et al. (2026) · Circuits Systems and Signal Processing · doi:10.1007/s00034-025-03480-4
“Against [2 ], this work achieves significant optimization in both supply voltage and power consumption which power consumption (2.96 µW ) is only 1/51 of 151.4 µW , with better linearity.”
InfluentialLiteWiFi: Ultra-low Power Wi-Fi Radio for Ubiquitous IoT Connection
Wang, B., Yang, Z., Li, W., et al. (2026) · doi:10.1109/infocom59046.2026.11571761
“Other designs operate at sampling rates of tens or hundreds of MHz while consuming between 150µW to 400µW [37]–[39].”
A sampled-data differentiator for time-mode signal processing
Bertsatou, A., Tsetsonis, A., Chronopoulou, A. I., et al. (2026) · AEU - International Journal of Electronics and Communications · doi:10.1016/j.aeue.2026.156555
Panetas-Felouris, O., Pagkalos, K. P., & Vlassis, S. (2026) · Circuits Systems and Signal Processing · doi:10.1007/s00034-026-03786-x
- Authors
- Campos, A. L., Navarro, J., Luppe, M., & de Lima, E. R.
- Affiliations
- Universidade de São Paulo (BR)
- Corresponding author
- Luppe, Maximiliam
- Venue
- Analog Integrated Circuits and Signal Processing
- Published
- 2021-01
- Volume
- 106
- Issue
- 1
- Pages
- 321-337
- ISSN
- 0925-1030 (ISSN-L)
- 1573-1979
- OpenAlex
- W3128291763
- Semantic Scholar
- 77b482fe1b8c8f16d78898582fc3d5a51c76f294
- Cited by
- 8
- References
- 31
- Citations by year
- 2026: 4 · 2025: 2 · 2024: 1 · 2021: 1
- FWCI
- 0.14
- Type
- journal article
- Language
- en
- Open access
- hybrid
- doi.org
- Locations
- Analog Integrated Circuits and Signal Processing (publishedVersion, cc-by)
- Topics
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
- Keywords
- successive approximation register ADC, asynchronous ADC, low-power analog-to-digital converter, 65 nm CMOS, differential input, energy efficiency, 10-bit resolution
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Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
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