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A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors
Abstract
Many artificial intelligence (AI) edge devices use nonvolatile memory (NVM) to store the weights for the neural network (trained off-line on an AI server), and require low-energy and fast I/O accesses. The deep neural networks (DNN) used by AI processors [1,2] commonly require p-layers of a convolutional neural network (CNN) and q-layers of a fully-connected network (FCN). Current DNN processors that use a conventional (von-Neumann) memory structure are limited by high access latencies, I/O energy consumption, and hardware costs. Large working data sets result in heavy accesses across the memory hierarchy, moreover large amounts of intermediate data are also generated due to the large number of multiply-and-accumulate (MAC) operations for both CNN and FCN. Even when binary-based DNN [3] are used, the required CNN and FCN operations result in a major memory I/O bottleneck for AI edge devices.
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Price, M., Glass, J., & Chandrakasan, A. P. (2017) · 2017 IEEE International Solid-State Circuits Conference (ISSCC) · doi:10.1109/isscc.2017.7870352 · Cited by 86
Su, F., Chen, W.-H., Xia, L., Lo, C.-P., Tang, T., Wang, Z., Hsu, K.-H., Cheng, M., Li, J.-Y., Xie, Y., et al. (2017) · 2017 Symposium on VLSI Technology · doi:10.23919/vlsit.2017.7998149 · Cited by 69
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Self-citationIn-Memory Computing: Advances and Prospects
Verma, N., Jia, H., Valavi, H., Tang, Y., Ozatay, M., Chen, L.-Y., Zhang, B., & Deaville, P. (2019) · IEEE Solid-State Circuits Magazine · doi:10.1109/mssc.2019.2922889 · Cited by 473
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Lin, P., Li, C., Wang, Z., Li, Y., Jiang, H., Song, W., Rao, M., Zhuo, Y., Upadhyay, N. K., Barnell, M., et al. (2020) · Nature Electronics · doi:10.1038/s41928-020-0397-9 · Cited by 375
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Valavi, H., Ramadge, P. J., Nestler, E., & Verma, N. (2019) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2019.2899730 · Cited by 328
Liu, Q., Gao, B., Yao, P., Wu, D., Chen, J., Pang, Y., Zhang, W., Liao, Y., Xue, C.-X., Chen, W.-H., et al. (2020) · 2020 IEEE International Solid- State Circuits Conference - (ISSCC) · doi:10.1109/isscc19947.2020.9062953 · Cited by 308
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Metadata
- Authors
- Chen, W.-H., Li, K.-X., Lin, W.-Y., Hsu, K.-H., Li, P.-Y., Yang, C.-H., Xue, C.-X., Yang, E.-Y., Chen, Y.-K., Chang, Y.-S., Hsu, T.-H., King, Y.-C., Lin, C.-J., Liu, R.-S., Hsieh, C.-C., Tang, K.-T., & Chang, M.-F.
- Venue
- 2018 IEEE International Solid - State Circuits Conference - (ISSCC)
- Publisher
- IEEE
- Published
- 2018-02
- Pages
- 494-496
- ISSN
- 0193-6530 (ISSN-L)
- OpenAlex
- W2794288888
- Cited by
- 333
- References
- 2
- FWCI
- 67.94
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Chen, W.-H., Li, K.-X., Lin, W.-Y., Hsu, K.-H., Li, P.-Y., Yang, C.-H., Xue, C.-X., Yang, E.-Y., Chen, Y.-K., Chang, Y.-S., Hsu, T.-H., King, Y.-C., Lin, C.-J., Liu, R.-S., Hsieh, C.-C., Tang, K.-T., & Chang, M.-F. (2018). A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors. 2018 IEEE International Solid - State Circuits Conference - (ISSCC). https://doi.org/10.1109/isscc.2018.8310400
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