14.4 A scalable speech recognizer with deep-neural-network acoustic models and voice-activated power gating

Kaldi Speech Recognition Toolkit

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A 0.3–2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets

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24.2 Context-aware hierarchical information-sensing in a 6μW 90nm CMOS voice activity detector

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A fixed-point neural network for keyword detection on resource constrained hardware

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Memory-Efficient Modeling and Search Techniques for Hardware ASR Decoders

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27.2 A 6mW 5K-Word real-time speech recognizer using WFST models

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Deep Learning for IoT Big Data and Streaming Analytics: A Survey

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Hardware implementation of memristor-based artificial neural networks

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A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors

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CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors

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Recent advances in efficient computation of deep convolutional neural networks

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A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array

Kang, M., Gonugondla, S. K., Patil, A. D., & Shanbhag, N. R. (2018) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2017.2782087 · Cited by 225 · see citing works

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors

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A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors

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ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration

Long, Y., Na, T., & Mukhopadhyay, S. (2018) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2018.2819190 · Cited by 123 · see citing works

A Low-Power Speech Recognizer and Voice Activity Detector Using Deep Neural Networks

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Vocell: A 65-nm Speech-Triggered Wake-Up SoC for 10-$\mu$ W Keyword Spotting and Speaker Verification

Giraldo, J. S. P., Lauwereins, S., Badami, K. M. H., & Verhelst, M. (2020) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2020.2968800 · Cited by 108 · see citing works

DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications

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Deep Learning–Based Noise Reduction Approach to Improve Speech Intelligibility for Cochlear Implant Recipients

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Design of an Always-On Deep Neural Network-Based 1-$\mu$ W Voice Activity Detector Aided With a Customized Software Model for Analog Feature Extraction

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Laika: A 5uW Programmable LSTM Accelerator for Always-on Keyword Spotting in 65nm CMOS

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A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor

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A 1μW voice activity detector using analog feature extraction and digital deep neural network

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An In-Memory VLSI Architecture for Convolutional Neural Networks

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17.2 A 142nW Voice and Acoustic Activity Detection Chip for mm-Scale Sensor Nodes Using Time-Interleaved Mixer-Based Frequency Scanning

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A 19.4-nJ/Decision, 364-K Decisions/s, In-Memory Random Forest Multi-Class Inference Accelerator

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±CIM SRAM for Signed In-Memory Broad-Purpose Computing From DSP to Neural Processing

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Compacting Deep Neural Networks for Internet of Things: Methods and Applications

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An Ultra-Low Power Binarized Convolutional Neural Network-Based Speech Recognition Processor With On-Chip Self-Learning

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Efficient Softmax Hardware Architecture for Deep Neural Networks

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A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network

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Real-Time Speech Recognition for IoT Purpose using a Delta Recurrent Neural Network Accelerator

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A Review on the Immediate Advancement of the Internet of Things in Wireless Telecommunications

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From Less Batteries to Battery-Less Alert Systems with Wide Power Adaptation down to nWs—Toward a Smarter, Greener World

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Improved LSTM-Based Abnormal Stream Data Detection and Correction System for Internet of Things

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Using hierarchical statistical analysis and deep neural networks to detect covert timing channels

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Trainer: An Energy-Efficient Edge-Device Training Processor Supporting Dynamic Weight Pruning

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A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting

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A 760-nW, 180-nm CMOS Fully Analog Voice Activity Detection System for Domestic Environment

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Optimized Hierarchical Cascaded Processing

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High-Throughput, Area-Efficient, and Variation-Tolerant 3-D In-Memory Compute System for Deep Convolutional Neural Networks

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Hardware Implementations for Voice Activity Detection: Trends, Challenges and Outlook

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A $1.5\mu\mathrm{W}$ End-to-End Keyword Spotting SoC with Content-Adaptive Frame Sub-Sampling and Fast-Settling Analog Frontend

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A High-Accuracy Implementation for Softmax Layer in Deep Neural Networks

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An Ultra-Low Power Always-On Keyword Spotting Accelerator Using Quantized Convolutional Neural Network and Voltage-Domain Analog Switching Network-Based Approximate Computing

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Deep In-Memory Architectures for Machine Learning–Accuracy Versus Efficiency Trade-Offs

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More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network

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Human-machine interaction in intelligent technologies using the augmented reality

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Low-Energy Voice Activity Detection via Energy-Quality Scaling From Data Conversion to Machine Learning

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A 108nW 0.8mm2 Analog Voice Activity Detector (VAD) Featuring a Time-Domain CNN as a Programmable Feature Extractor and a Sparsity-Aware Computational Scheme in 28nm CMOS

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ElectrodeNet—A Deep-Learning-Based Sound Coding Strategy for Cochlear Implants

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EERA-KWS: A 163 TOPS/W Always-on Keyword Spotting Accelerator in 28nm CMOS Using Binary Weight Network and Precision Self-Adaptive Approximate Computing

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Hardware Acceleration for Embedded Keyword Spotting: Tutorial and Survey

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A shared synapse architecture for efficient FPGA implementation of autoencoders

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A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random Access Memory (ReRAM)-Based Computing-in-Memory

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KeyRAM: A 0.34 uJ/decision 18 k decisions/s Recurrent Attention In-memory Processor for Keyword Spotting

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A STT-Assisted SOT MRAM-Based In-Memory Booth Multiplier for Neural Network Applications

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A Hardware-Oriented and Memory-Efficient Method for CTC Decoding

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A 1D-CRNN Inspired Reconfigurable Processor for Noise-robust Low-power Keywords Recognition

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A 28-nm 1.3-mW Speech-to-Text Accelerator for Edge AI Devices

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QCNN Inspired Reconfigurable Keyword Spotting Processor With Hybrid Data-Weight Reuse Methods

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Flexible Low Power CNN Accelerator for Edge Computing with Weight Tuning

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A Low-Power Streaming Speech Enhancement Accelerator for Edge Devices

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Quality Driven Systematic Approximation for Binary-Weight Neural Network Deployment

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Evaluating the Impact of Fault-Tolerance Capability of Deep Neural Networks Caused by Faults

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An Ultra-low Power RNN Classifier for Always-On Voice Wake-Up Detection Robust to Real-World Scenarios

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Energy-Efficient Recurrent Neural Network With MRAM-Based Probabilistic Activation Functions

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Negative capacitance FET based dual-split control 6T-SRAM cell design for energy efficient and robust computing-in memory architectures

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Binarized Weight Neural-Network Inspired Ultra-Low Power Speech Recognition Processor with Time-Domain Based Digital-Analog Mixed Approximate Computing

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A 760 nW, 180 nm CMOS Analog Voice Activity Detection System

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A Background Noise Self-adaptive VAD Using SNR Prediction Based Precision Dynamic Reconfigurable Approximate Computing

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A 28.5µW All-Analog Voice-Activity Detector

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An On-Chip Trainable and Scalable In-Memory ANN Architecture for AI/ML Applications

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A 34.7 µW Speech Keyword Spotting IC Based on Subband Energy Feature Extraction

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A Survey on Data Stream Mining Towards the Internet of Things Application

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Cascaded Classifier for Pareto-Optimal Accuracy-Cost Trade-Off Using Off-the-Shelf ANNs

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Energy-Efficient Speaker Identification with Low-Precision Networks

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Optimized Hierarchical Cascaded Processing

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A 1.3mW Speech-to-Text Accelerator with Bidirectional Light Gated Recurrent Units for Edge AI

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Deep learning chips

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Voice Activity Detection with >83% Accuracy under SNR down to −3dB at $1.19\mu \mathrm{W}$ and 0.07mm2 in 40nm

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Exploring the Use of Hierarchal Statistical Analysis and Deep Neural Networks to Detect and Mitigate Covert Timing Channels

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Algorithms and low power hardware for keyword spotting

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OpenPaaS::NG: A Cloud-Based Interoperable Enterprise Platform to Support Inter-organizational Collaborations

Zribi, S., & Lorré, J.-P. (2019) · Proceedings of the I-ESA Conference · doi:10.1007/978-3-030-13693-2_9

Energy-Quality Scalable Analog-to-Digital Conversion and Machine Learning Engine in a 51.9 nJ/frame Voice Activity Detector

Teo, J. H., Cheng, S., & Alioto, M. (2019) · IEEE International Conference on Electronics, Circuits and Systems (ICECS) · doi:10.1109/icecs46596.2019.8964767

In-memory Implementation of On-chip Trainable and Scalable ANN for AI/ML ApplicationsPreprint

Kumar, A., Singh, J., Beeraka, S. M., & Gupta, B. (2020) · arXiv (Cornell University) · doi:10.48550/arxiv.2005.09526

Data Management and Mining Technologies to Manage and Analyze Data in IoT

Sharma, S., Sasubilli, S. M., & Bhargava, K. (2020) · Swarm Intelligence Optimization · doi:10.1002/9781119778868.ch10

Swarm Intelligence for Data Management and Mining Technologies to Manage and Analyze Data in IoT

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Big Data Search Engines and Deep Computers

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A Chronic Diseases Detection Integrated Interface With Anti-Drift Normalization and On-Chip Classification Schemes

Yeom, J., Song, M., Choi, J. H., Pyeon, Y. J., Cho, J., Kim, H., Cho, S., Lee, Y.-S., Lee, Y. J., & Kim, J. J. (2025) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2025.3547720

A Low-Power Speech Recognizer and Voice Activity Detector Using Deep Neural Networks

Price, M., Glass, J. R., & Chandrakasan, A. P. (2017) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2017.2752838 · Cited by 118 · see citing works

A Low-Power, High-Performance Speech Recognition Accelerator

Yazdani, R., Arnau, J.-M., & González, A. M. (2019) · IEEE Transactions on Computers · doi:10.1109/tc.2019.2937075 · Cited by 19 · see citing works

Design and Evaluation of an Ultra Low-power Human-quality Speech Recognition System

Rivero, D. P., Arnau, J.-M., & González, A. M. (2020) · ACM Transactions on Architecture and Code Optimization · doi:10.1145/3425604 · Cited by 5 · see citing works

Voice Activity Detection with >83% Accuracy under SNR down to −3dB at $1.19\mu \mathrm{W}$ and 0.07mm2 in 40nm

Teo, J. H., Ali, K., & Alioto, M. (2020) · IEEE Asian Solid-State Circuits Conference (A-SSCC) · doi:10.1109/a-sscc48613.2020.9336132 · Cited by 1 · see citing works

An ultra low-power hardware accelerator for automatic speech recognition

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