16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications
Abstract
From the cloud to edge devices, artificial intelligence (AI) and machine learning (ML) are widely used in many cognitive tasks, such as image classification and speech recognition. In recent years, research on hardware accelerators for AI edge devices has received more attention, mainly due to the advantages of AI at the edge: including privacy, low latency, and more reliable and effective use of network bandwidth. However, traditional computing architectures (such as CPUs, GPUs, FPGAs, and even existing AI accelerator ASICs) cannot meet the future needs of energy-constrained AI edge applications. This is because ML computing is data-centric, most of the energy in these architectures is consumed by memory accesses. In order to improve energy efficiency, both academia and industry are exploring a new computing architecture, namely compute in memory (CIM). CIM research is focused on a more analog approach with high-energy efficiency; however, lack of accuracy, due to a low SNR, is the main disadvantage; therefore, an analog approach may not be suitable for some applications that require high accuracy.
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Most compute-in-memory or near-memory approaches based on SRAMs and digital compute do not address the energy and time costs of reloading weights, making direct side-by-side comparisons against NVM-based weight-stationary approaches difficult; several NVM compute-in-memory studies have focused on the macro-level without accounting for data transport, control or chip infrastructure costs, and are,
“Although several compute-in-memory or near-memory approaches based on SRAMs and digital compute35–38 have been presented in the literature, most of these do not address the energy and time costs of reloading weights, thus making direct side-by-side comparisons against NVM-based weight-stationary approaches difficult.”
From An analog-AI chip for energy-efficient speech recognition and transcription (2023) · cites this paper as [37]
Cites
Biswas, A., & Chandrakasan, A. P. (2018) · 2018 IEEE International Solid - State Circuits Conference - (ISSCC) · doi:10.1109/isscc.2018.8310397 · Cited by 337 · see citing works
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An analog-AI chip for energy-efficient speech recognition and transcription
Ambrogio, S., Narayanan, P., Okazaki, A., Fasoli, A., Mackin, C., Hosokawa, K., Nomura, A., Yasuda, T., Chen, A., Friz, A., et al. (2023) · Nature · doi:10.1038/s41586-023-06337-5 · Cited by 242 · see citing works
Fusion of memristor and digital compute-in-memory processing for energy-efficient edge computing
Wen, T.-H., Hung, J.-M., Huang, W.-H., Jhang, C.-J., Lo, Y.-C., Hsu, H.-H., Ke, Z.-E., Chen, Y.-C., Chin, Y.-H., Su, C.-I., et al. (2024) · Science · doi:10.1126/science.adf5538 · Cited by 131 · see citing works
Self-citationAn ADC-Less RRAM-Based Computing-in-Memory Macro With Binary CNN for Efficient Edge AI
Li, Y., Chen, J., Wang, L., Zhang, W., Guo, Z., Wang, J., Han, Y., Li, Z., Wang, F., Dou, C., et al. (2023) · IEEE Transactions on Circuits and Systems II: Express Briefs · doi:10.1109/tcsii.2022.3233396 · Cited by 34 · see citing works
- Authors
- Chih, Y.-D., Lee, P.-H., Fujiwara, H., Shih, Y.-C., Lee, C.-F., Naous, R., Chen, Y.-L., Lo, C.-P., Lu, C.-H., Mori, H., Zhao, W.-C., Sun, D., Sinangil, M. E., Chen, Y.-H., Chou, T.-L., Akarvardar, K., Liao, H.-J., Wang, Y., Chang, M.-F., & Chang, T.-Y. J.
- Affiliations
- Taiwan Semiconductor Manufacturing Company (Taiwan) (TW)
- TSMC,Hsinchu,Taiwan
- ORCID
- Venue
- 2021 IEEE International Solid- State Circuits Conference (ISSCC)
- Publisher
- IEEE
- Published
- 2021-02-13
- Pages
- 252-254
- ISSN
- 0193-6530 (ISSN-L)
- OpenAlex
- W3134526034
- Cited by
- 384
- References
- 1
- Citations by year
- 2026: 64 · 2025: 126 · 2024: 79 · 2023: 60 · 2022: 47 · 2021: 8
- FWCI
- 76.14
- Type
- conference paper
- Language
- en
- Open access
- closed
- Licence
- Locations
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Keywords
- in-memory computing, machine learning accelerators, edge computing, energy efficiency, memory access energy, 22nm CMOS, hardware accelerators
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