Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications
Open accessAbstract
Convolutional neural networks (CNN) provide state-of-the-art results in a wide variety of machine learning (ML) applications, ranging from image classification to speech recognition. However, they are very computationally intensive and require huge amounts of storage. Recent work strived towards reducing the size of the CNNs: [1] proposes a binary-weight-network (BWN), where the filter weights (wi's) are ±1 (with a common scaling factor per filter: α). This leads to a significant reduction in the amount of storage required for the Wi's, making it possible to store them entirely on-chip. However, in a conventional all-digital implementation [2, 3], reading the wjis and the partial sums from the embedded SRAMs require a lot of data movement per computation, which is energy-hungry. To reduce data-movement, and associated energy, we present an SRAM-embedded convolution architecture (Fig. 31.1.1), which does not require reading the wi's explicitly from the memory. Prior work on embedded ML classifiers have focused on 1b outputs [4] or a small number of output classes [5], both of which are not sufficient for CNNs. This work uses 7b inputs/outputs, which is sufficient to maintain good accuracy for most of the popular CNNs [1]. The convolution operation is implemented as voltage averaging (Fig. 31.1.1), since the wj's are binary, while the averaging factor (1/N) implements the weight-coefficient α (with a new scaling factor, M, implemented off-chip).
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Most compute-in-memory or near-memory approaches based on SRAMs and digital compute do not address the energy and time costs of reloading weights, making direct side-by-side comparisons against NVM-based weight-stationary approaches difficult; several NVM compute-in-memory studies have focused on the macro-level without accounting for data transport, control or chip infrastructure costs, and are,
“Although several compute-in-memory or near-memory approaches based on SRAMs and digital compute35–38 have been presented in the literature, most of these do not address the energy and time costs of reloading weights, thus making direct side-by-side comparisons against NVM-based weight-stationary approaches difficult.”
From An analog-AI chip for energy-efficient speech recognition and transcription (2023) · cites this paper as [32]
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- Authors
- Biswas, A., & Chandrakasan, A. P.
- Affiliations
- Massachusetts Institute of Technology (US)
- Venue
- 2018 IEEE International Solid - State Circuits Conference - (ISSCC)
- Publisher
- IEEE
- Published
- 2018-02
- Volume
- 2018
- Pages
- 488-490
- ISSN
- 0193-6530 (ISSN-L)
- OpenAlex
- W2792893539
- Semantic Scholar
- ba28ee795de7c88258053fb31aef198c18b2cd5a
- Cited by
- 337
- References
- 7
- Citations by year
- 2026: 8 · 2025: 13 · 2024: 35 · 2023: 50 · 2022: 55 · 2021: 50 · 2020: 63 · 2019: 50 · 2018: 13
- FWCI
- 70.19
- Type
- conference paper
- Language
- en
- Open access
- green
- hdl.handle.net
- Licence
- cc-by-nc-sa
- Locations
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference (publishedVersion)
- DSpace@MIT (Massachusetts Institute of Technology) (submittedVersion, cc-by-nc-sa)
- IEEE Conference Proceedings
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Keywords
- data movement reduction
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