A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
Abstract
This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13-¿m 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 dB and consumes 0.826 mW, resulting in a figure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only 195 × 265 ¿m2.
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Latch offset, when the common-mode voltage is kept constant, is not affected by input values, is almost time invariant, and slightly influences ADC linearity.
“In fact, the latch offset, when the common-mode voltage is kept constant, is not affected by the input values and, in consequence, is almost time invariant and slightly influence the ADC linearity [16].”
From A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS (2021) · cites this paper as [16]
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Han, D., Zheng, Y., Rajkumar, R., Dawe, G. S., & Je, M. (2013) · IEEE Transactions on Biomedical Circuits and Systems · doi:10.1109/tbcas.2014.2298860 · Cited by 147 · see citing works
Recent Trends and Future Prospects of Neural Recording Circuits and Systems: A Tutorial Brief
Chen, J., Tarkhan, M., Wu, H., Noshahr, F. H., Yang, J., & Sawan, M. (2022) · IEEE Transactions on Circuits and Systems II: Express Briefs · doi:10.1109/tcsii.2022.3171689 · Cited by 38 · see citing works
A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS
Campos, A. L., Navarro, J., Luppe, M., & de Lima, E. R. (2021) · Analog Integrated Circuits and Signal Processing · doi:10.1007/s10470-020-01742-6 · Cited by 8 · see citing works
- Authors
- Liu, C.-C., Chang, S.-J., Huang, G.-Y., & Lin, Y.-Z.
- Affiliations
- National Cheng Kung University (TW)
- Venue
- IEEE Journal of Solid-State Circuits
- Published
- 2010-04
- Volume
- 45
- Issue
- 4
- Pages
- 731-740
- ISSN
- 0018-9200 (ISSN-L)
- 1558-173X
- OpenAlex
- W2101004723
- Cited by
- 1,329
- References
- 0
- Citations by year
- 2026: 53 · 2025: 98 · 2024: 89 · 2023: 98 · 2022: 90 · 2021: 87 · 2020: 77 · 2019: 107 · 2018: 104 · 2017: 93 · 2016: 110 · 2015: 92 · 2014: 99 · 2013: 65 · 2012: 42
- FWCI
- 24.92
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- IEEE Journal of Solid-State Circuits (publishedVersion)
- Topics
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Keywords
- successive approximation register ADC, comparator offset cancellation, low-power analog-to-digital converter
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