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An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput

Kawahara, Akifumi, Azuma, Ryotaro, Ikeda, Yuuichirou, Kawai, Ken, Katoh, Yoshikazu, Hayakawa, Yukio, Tsuji, Kiyotaka, Yoneda, Shinichi, Himeno, Atsushi, Shimakawa, Kazuhiko, Takagi, Takeshi, Mikawa, Takumi, Aono, Kunitoshi·2013·IEEE Journal of Solid-State Circuits

Abstract

An 8-Mb multi-layered cross-point resistive RAM (ReRAM) macro has been developed with 443 MB/s write throughput (64-bits parallel write per 17.2-ns cycle), which is almost twice as fast as competing methods. It uses the fast switching performance of TaOx ReRAM and a new write architecture to reduce the sneak current in a cross-point cell array structure based on an 0.18-μm process. First, a bidirectional diode as a memory cell select element is developed to reduce the sneak current. Second, PMOS and NMOS are used select transistors in the source follower to realize stable switching for the selected cell in the multi-layered cross-point structure. Third, a hierarchical bitline (BL) structure is employed with a short bitline. Fourth, multi-bit write architecture is developed to realize fast write operation and to suppress the sneak current.

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Metadata

Authors
Kawahara, A., Azuma, R., Ikeda, Y., Kawai, K., Katoh, Y., Hayakawa, Y., Tsuji, K., Yoneda, S., Himeno, A., Shimakawa, K., Takagi, T., Mikawa, T., & Aono, K.
Venue
IEEE Journal of Solid-State Circuits
Published
2013-01
Volume
48
Issue
1
Pages
178-185
ISSN
  • 0018-9200 (ISSN-L)
  • 1558-173X
OpenAlex
W2178102281
Cited by
310
References
0
FWCI
17.91
Type
journal article
Language
en
Open access
closed

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The paper
Kawahara, A., Azuma, R., Ikeda, Y., Kawai, K., Katoh, Y., Hayakawa, Y., Tsuji, K., Yoneda, S., Himeno, A., Shimakawa, K., Takagi, T., Mikawa, T., & Aono, K. (2013). An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput. IEEE Journal of Solid-State Circuits. https://doi.org/10.1109/jssc.2012.2215121

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