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Cited by 244Low-power high-performance VLSI designAdvanced Memory and Neural ComputingParallel Computing and Optimization Techniques

The DOI matches its Crossref record; 5 of the 5 references it cites were found in a registry or an index.

A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing

Wang, Jingcheng, Wang, Xiaowei, Eckert, Charles, Subramaniyan, Arun, Das, Reetuparna, Blaauw, David, Sylvester, Dennis·2020·IEEE Journal of Solid-State Circuits
DOI 10.1109/jssc.2019.2939682
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Abstract

This article proposes a general-purpose hybrid in-/near-memory compute SRAM (CRAM) that combines an 8T transposable bit cell with vector-based, bit-serial in-memory arithmetic to accommodate a wide range of bit-widths, from single to 32 or 64 bits, as well as a complete set of operation types, including integer and floating-point addition, multiplication, and division. This approach provides the flexibility and programmability necessary for evolving software algorithms ranging from neural networks to graph and signal processing. The proposed design was implemented in a small Internet of Things (IoT) processor in the 28-nm CMOS consisting of a Cortex-M0 CPU and 8 CRAM banks of 16 kB each (128 kB total). The system achieves 475-MHz operation at 1.1 V and, with all CRAMs active, produces 30 GOPS or 1.4 GFLOPS on 32-bit operands. It achieves an energy efficiency of 0.56 TOPS/W for 8-bit multiplication and 5.27 TOPS/W for 8-bit addition at 0.6 V and 114 MHz.

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Crossref · 10.1109/jssc.2019.2939682

Cites

5 of 5 references verified0 citation errors · 0 not checkable

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  • Processing in-static/dynamic RAM has recently been studied as an in-memory computing paradigm to tackle the data movement (von Neumann) bottleneck in modern computing systems.

    “SRAM and DRAM, for example, are commercially applied in CPUs for storage in multiple hierarchy levels, from the cache to the main memory [150]; thus, as Table 1 indicates, processing in-static/dynamic RAM has recently been studied as an in-memory computing paradigm to tackle the data movement (von Neumann) bottleneck in modern computing systems.”

    From Brain-inspired computing systems: a systematic literature review (2024) · cites this paper as [150]

Citations

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Research works printed but not linked: 31

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  30. denyer, 1985, VLSI Signal Processing A Bit-Serial Approach
  31. 10.1109/TC.1982.1676015 · DOI

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Metadata

Authors
Wang, J., Wang, X., Eckert, C., Subramaniyan, A., Das, R., Blaauw, D., & Sylvester, D.
Affiliations
University of Michigan (US)
ORCID
Venue
IEEE Journal of Solid-State Circuits
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Published
2020-01
Volume
55
Issue
1
Pages
76-86
ISSN
  • 0018-9200 (ISSN-L)
  • 1558-173X
DOI
10.1109/jssc.2019.2939682
OpenAlex
W2976137532
Cited by
244
References
5
Citations by year
2026: 29 · 2025: 48 · 2024: 42 · 2023: 55 · 2022: 32 · 2021: 25 · 2020: 13
FWCI
6.29
Type
journal article
Language
en
Open access
closed
Licence
Locations
IEEE Journal of Solid-State Circuits (publishedVersion)
Funders
Semiconductor Research Corporation
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
  • Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
Keywords
in-memory computing, near-memory computing, bit-serial arithmetic, 8T SRAM, 28nm CMOS, energy efficiency, neural network hardware

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