A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS
Abstract
A single-chip, bidirectional brain-computer interface (BBCI) enables neuromodulation through simultaneous neural recording and stimulation. This article presents a prototype BBCI application-specified integrated circuit (ASIC) consisting of a 64-channel time-multiplexed recording frontend, an area-optimized four-channel high-voltage compliant stimulator, and electronics to support the concurrent multichannel stimulus artifact cancellation. Stimulator power generation is integrated on a chip, providing ±11-V compliance from low-voltage supplies with a resonant charge pump. Highfrequency (~3 GHz) self-resonant clocking is used to reduce the pumping capacitor area while suppressing the associated switching losses. A 32-tap least mean square (LMS)-based digital adaptive filter achieves 60-dB artifact suppression, enabling simultaneous neural stimulation and recording. The entire chip occupies 4 mm2in a 65-nm low power (LP) process and is powered by 2.5-/1.2-V supplies, dissipating 205 μW in recording and 142 μW in the stimulation and cancellation back-ends. The stimulation output drivers achieve 31% dc-dc efficiency at a maximum output power of 24 mW.
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Dynamic bulk biasing techniques have been studied to enable a higher stimulator compliance voltage that is not limited by the diode breakdown level with the aid of charge pumps.
“In addition to the implementation of thick-oxide devices to achieve a fully isolated active output [140], [150], dynamic bulk biasing techniques have been studied to enable a higher stimulator compliance voltage [151] that is not limited by the diode breakdown level with the aid of charge pumps [152].”
From Active Neural Interface Circuits and Systems for Selective Control of Peripheral Nerves: A Review (2024) · cites this paper as [152]
A hybrid approach is often adopted that combines multiple structures for effective artifact detection and cancellation while adhering to the system power and area constraints.
“A hybrid approach is often adopted that combines multiple structures for effective artifact detection and cancellation while adhering to the system power and area constraints [152], [192], [193].”
From Active Neural Interface Circuits and Systems for Selective Control of Peripheral Nerves: A Review (2024) · cites this paper as [152]
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References 36 · Cited by 81
- Authors
- Uehlin, J. P., Smith, W. A., Pamula, V. R., Pepin, E. P., Perlmutter, S., Sathe, V., & Rudell, J. C.
- Affiliations
- SpaceX (United States) (US)
- University of Washington (US)
- ORCID
- Venue
- IEEE Journal of Solid-State Circuits
- Published
- 2020-07
- Volume
- 55
- Issue
- 7
- Pages
- 1749-1761
- ISSN
- 0018-9200 (ISSN-L)
- 1558-173X
- OpenAlex
- W3025507103
- Cited by
- 81
- References
- 36
- Citations by year
- 2026: 5 · 2025: 16 · 2024: 17 · 2023: 15 · 2022: 17 · 2021: 10 · 2020: 1
- FWCI
- 3.38
- Type
- journal article
- Language
- en
- Open access
- closed
- Licence
- Locations
- IEEE Journal of Solid-State Circuits (publishedVersion)
- Funders
- Medtronic and the Center for Neurotechnology, under NSF Award Number (EEC-1028725)
- Topics
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Life Sciences › Neuroscience › Cellular and Molecular Neuroscience › Neuroscience and Neural Engineering
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
- Keywords
- neural recording, high-voltage stimulation, artifact removal, neuromodulation, CMOS ASIC, LMS adaptive filter, low-power integrated circuits, 65 nm CMOS
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