The DOI matches its Crossref record; 31 of the 32 references it cites were found in a registry or an index.
A Dual-Polarization Silicon-Photonic Coherent Receiver Front-End Supporting 528 Gb/s/Wavelength
Abstract
Supporting advanced modulation schemes such as 16 quadrature-amplitude modulation (QAM) in a high-speed transimpedance amplifier (TIA) requires minimizing noise and total harmonic distortion (THD) across gain settings and frequency. Accordingly, our automatically reconfigurable TIA reduces base resistor noise, gain peaking, phase margin (PM) degradation, and$f_{T}$degradation, operating on a single sense voltage and eliminating the need for multiple control loops. A collaborative offset and dc current cancellation technique is introduced to reduce offset-induced nonlinearity, while protecting the receiver (RX) against current overdrive. A prototype of the RX is fabricated on 130-nm SiGe BiCMOS process and demonstrates a maximum gain of 75.5 dB$\Omega $with 35.5 dB of dynamic range, 42-GHz bandwidth (BW), and a maximum gain averaged input-referred noise (IRN) of 18.5 pA/$\sqrt {\text {Hz}}$. The silicon-photonic transceiver assembly incorporating four such RXs achieves 25-dB required optical signal to noise ratio (ROSNR) for received optical power between–22 and 1 dBm at 50 Gbaud, and aggregate data rate of 528 Gb/s/$\lambda$at 66 Gbaud and 25-dB ROSNR.
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Linearity requirements for the TIAs and drivers are more stringent for coherent transceivers.
“Linearity requirements for the TIAs and drivers are more stringent137,144”
From Roadmapping the next generation of silicon photonics (2024) · cites this paper as [137]
Most of the silicon photonic transceivers in HVM today are based on a 2.5D integration approach, where the PIC and EIC(s) are designed, sized, optimized, tested in their best respective processes, and then flip-chipped to an interposer substrate.
“Most of the silicon photonic transceivers in HVM today are based on a 2.5D integration approach, where the PIC and EIC(s) are designed, sized, optimized, tested in their best respective processes, and then flip-chipped to an interposer substrate17,19,24,25,137”
From Roadmapping the next generation of silicon photonics (2024) · cites this paper as [137]
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Self-citation
Metadata
- Authors
- Ahmed, A. H., Vera, L., Iotti, L., Shi, R., Shekhar, S., & Rylyakov, A.
- Affiliations
- University of British Columbia (CA)
- Nokia, New York City, NY, USA
- Venue
- IEEE Journal of Solid-State Circuits
- Published
- 2023-08
- Volume
- 58
- Issue
- 8
- Pages
- 2202-2213
- ISSN
- 0018-9200 (ISSN-L)
- 1558-173X
- OpenAlex
- W4352977352
- Cited by
- 18
- References
- 32
- Citations by year
- 2026: 4 · 2025: 4 · 2024: 8 · 2023: 2
- FWCI
- 1.34
- Type
- journal article
- Language
- en
- Open access
- closed
- Licence
- Locations
- IEEE Journal of Solid-State Circuits (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Photonic Communication Systems
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Photonic and Optical Devices
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Optical Network Technologies
- Keywords
- silicon photonics, coherent optical receivers, transimpedance amplifier, dual polarization, 16-QAM, offset cancellation, current cancellation, input-referred noise, phase margin, high-speed optical transmission
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