The DOI matches its Crossref record; 1 of the 1 references it cites were found in a registry or an index.
Ramulator: A Fast and Extensible DRAM Simulator
Open accessAbstract
Recently, both industry and academia have proposed many different roadmaps for the future of DRAM. Consequently, there is a growing need for an extensible DRAM simulator, which can be easily modified to judge the merits of today's DRAM standards as well as those of tomorrow. In this paper, we present Ramulator, a fast and cycle-accurate DRAM simulator that is built from the ground up for extensibility. Unlike existing simulators, Ramulator is based on a generalized template for modeling a DRAM system, which is only later infused with the specific details of a DRAM standard. Thanks to such a decoupled and modular design, Ramulator is able to provide out-of-the-box support for a wide array of DRAM standards: DDR3/4, LPDDR3/4, GDDR5, WIO1/2, HBM, as well as some academic proposals (SALP, AL-DRAM, TL-DRAM, RowClone, and SARP). Importantly, Ramulator does not sacrifice simulation speed to gain extensibility: according to our evaluations, Ramulator is 2.5× faster than the next fastest simulator. Ramulator is released under the permissive BSD license.
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Binkert, N., Beckmann, B., Black, G., Reinhardt, S. K., Saidi, A., Basu, A., Hestness, J., Hower, D. R., Krishna, T., Sardashti, S., et al. (2011) · ACM SIGARCH Computer Architecture News · doi:10.1145/2024716.2024718 · Cited by 4,930
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Metadata
- Authors
- Kim, Y., Yang, W., & Mutlu, O.
- Venue
- IEEE Computer Architecture Letters
- Published
- 2016-01-01
- Volume
- 15
- Issue
- 1
- Pages
- 45-49
- ISSN
- 1556-6056 (ISSN-L)
- OpenAlex
- W2034861439
- Cited by
- 764
- References
- 1
- FWCI
- 67.85
- Type
- journal article
- Language
- en
- Open access
- green
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