The DOI matches its Crossref record; 88 of the 88 references it cites were found in a registry or an index.
Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology
Abstract
Many important applications trigger bulk bitwise operations, i.e., bitwise operations on large bit vectors. In fact, recent works design techniques that exploit fast bulk bitwise operations to accelerate databases (bitmap indices, BitWeaving) and web search (BitFunnel). Unfortunately, in existing architectures, the throughput of bulk bitwise operations is limited by the memory bandwidth available to the processing unit (e.g., CPU, GPU, FPGA, processing-in-memory).
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Citations
Cites
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ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars
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Self-citation
Cited by
Memory devices and applications for in-memory computing
Sebastian, A., Le Gallo, M., Khaddam-Aljameh, R., & Eleftheriou, E. (2020) · Nature Nanotechnology · doi:10.1038/s41565-020-0655-z · Cited by 2,289
SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices
Kingra, S. K., Parmar, V., Chang, C.-C., Hudec, B., Hou, T.-H., & Suri, M. (2020) · Scientific Reports · doi:10.1038/s41598-020-59121-0 · Cited by 1,439
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks
Eckert, C., Wang, X., Wang, J., Subramaniyan, A., Iyer, R., Sylvester, D., Blaaauw, D., & Das, R. (2018) · 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA) · doi:10.1109/isca.2018.00040 · Cited by 369
A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute
Valavi, H., Ramadge, P. J., Nestler, E., & Verma, N. (2019) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2019.2899730 · Cited by 328
Spintronics for Energy- Efficient Computing: An Overview and Outlook
Guo, Z., Yin, J., Bai, Y., Zhu, D., Shi, K., Wang, G., Cao, K., & Zhao, W. (2021) · Proceedings of the IEEE · doi:10.1109/jproc.2021.3084997 · Cited by 304
Metadata
- Authors
- Seshadri, V., Lee, D., Mullins, T., Hassan, H., Boroumand, A., Kim, J., Kozuch, M. A., Mutlu, O., Gibbons, P. B., & Mowry, T. C.
- Venue
- Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture
- Publisher
- ACM
- Published
- 2017-10-14
- Pages
- 273-287
- ISSN
- 1072-4451 (ISSN-L)
- OpenAlex
- W2766489088
- Cited by
- 434
- References
- 88
- FWCI
- 37.92
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Seshadri, V., Lee, D., Mullins, T., Hassan, H., Boroumand, A., Kim, J., Kozuch, M. A., Mutlu, O., Gibbons, P. B., & Mowry, T. C. (2017). Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology. Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture. https://doi.org/10.1145/3123939.3124544
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Bibliographic data: Semantic Scholar, OpenAlex, Crossref.
Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.
