RAMP: Research Accelerator for Multiple Processors
Abstract
The RAMP project's goal is to enable the intensive, multidisciplinary innovation that the computing industry will need to tackle the problems of parallel processing. RAMP itself is an open-source, community-developed, FPGA-based emulator of parallel architectures. its design framework lets a large, collaborative community develop and contribute reusable, composable design modules. three complete designs - for transactional memory, distributed systems, and distributed-shared memory - demonstrate the platform's potential.
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The SimpleScalar tool set, version 2.0
Burger, D., & Austin, T. M. (1997) · ACM SIGARCH Computer Architecture News · doi:10.1145/268806.268810 · Cited by 3,058 · see citing works
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
Martin, M. M. K., Sorin, D. J., Beckmann, B. M., et al. (2005) · ACM SIGARCH Computer Architecture News · doi:10.1145/1105734.1105747 · Cited by 1,560 · see citing works
The M5 Simulator: Modeling Networked Systems
Binkert, N. L., Dreslinski, R., Hsu, L. R., et al. (2006) · IEEE Micro · doi:10.1109/mm.2006.82 · Cited by 848 · see citing works
Wunderlich, R. E., Wenisch, T. F., Falsafi, B., et al. (2003) · Proceedings - International Symposium on Computer Architecture/Proceedings · doi:10.1145/859618.859629 · Cited by 511 · see citing works
Complete computer system simulation: the SimOS approach
Rosenblum, M., Herrod, S. A., Witchel, E., et al. (1995) · IEEE Parallel & Distributed Technology Systems & Applications · doi:10.1109/88.473612 · Cited by 500 · see citing works
Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications
Sherwood, T., Perelman, E., & Calder, B. (2001) · Cited by 480 · see citing works
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
KleinOsowski, A. J., & Lilja, D. J. (2002) · IEEE Computer Architecture Letters · doi:10.1109/l-ca.2002.8 · Cited by 365 · see citing works
Basic block distribution analysis to find periodic behavior and simulation points in applications
Sherwood, T., Perelman, E., & Calder, B. (2002) · International Conference on Parallel Architectures and Compilation Techniques · doi:10.1109/pact.2001.953283 · Cited by 317 · see citing works
BEE2 A High-End Reconfigurable Computing System
Chen, C., Wawrzynek, J., & Brodersen, R. W. (2005) · IEEE Design & Test of Computers · doi:10.1109/mdt.2005.30 · Cited by 268 · see citing works
Self-citationAsim: a performance model framework
Emer, J., Ahuja, P., Borch, E., et al. (2002) · Computer · doi:10.1109/2.982918 · Cited by 223 · see citing works
Programming with transactional coherence and consistency (TCC)
Hammond, L., Carlstrom, B. D., Wong, V., et al. (2004) · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · doi:10.1145/1024393.1024395 · Cited by 149 · see citing works
RSIM Reference Manual: Version 1.0
Pai, V. S., Ranganathan, S., & Adve, S. V. (1997) · Rice Research Repository (Rice University) · Cited by 125 · see citing works
Network-Oriented Full-System Simulation using M5
Binkert, N. L. (2003) · Medical Entomology and Zoology · Cited by 111 · see citing works
SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling
Wunderlich, R. E., Wenisch, T. F., Falsafi, B., et al. (2004) · Proceedings - International Symposium on Computer Architecture/Proceedings · doi:10.1109/isca.2003.1206991 · Cited by 88 · see citing works
A practical FPGA-based framework for novel CMP research
Wee, S., Casper, J., Njoroge, N., et al. (2007) · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · doi:10.1145/1216919.1216936 · Cited by 59 · see citing works
Adl-Tabatabai, A.-R., Kozyrakis, C., & Saha, B. (2006) · Queue · doi:10.1145/1189276.1189288 · Cited by 59 · see citing works
Self-citationÖner, K., Barroso, L. A., Iman, S., et al. (1995) · doi:10.1145/201310.201321 · Cited by 18 · see citing works
Transactional programming in a multi-core environment
Adl-Tabatabai, A.-R., Kozyrakis, C., & Saha, B. (2007) · ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming · doi:10.1145/1229428.1229484 · Cited by 14 · see citing works
Self-citationThe Design of RPM: An FPGA-based Multiprocessor Emulator
Oner, K., Barroso, L. A., Iman, S., et al. (1995) · doi:10.1109/fpga.1995.241946 · Cited by 7 · see citing works
The Software Stack for Transactional Memory Challenges and Opportunities
Carlstrom, B. D., Chung, J., Kozyrakis, C., et al. (2006) · Cited by 1 · see citing works
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A view of the parallel computing landscape
Asanovic, K., Bodik, R., Demmel, J., Keaveny, T., Keutzer, K., Kubiatowicz, J., Morgan, N., Patterson, D., Sen, K., Wawrzynek, J., et al. (2009) · Communications of the ACM · doi:10.1145/1562764.1562783 · Cited by 627 · see citing works
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- Authors
- Wawrzynek, J., Patterson, D., Oskin, M., Lu, S.-L., Kozyrakis, C., Hoe, J. C., Chiou, D., & Asanovic, K.
- Affiliations
- University of California, Berkeley (US)
- University of Washington (US)
- Intel (United States) (US)
- Stanford University (US)
- Carnegie Mellon University (US)
- The University of Texas at Austin (US)
- Venue
- IEEE Micro
- Published
- 2007-03
- Volume
- 27
- Issue
- 2
- Pages
- 46-57
- ISSN
- 0272-1732 (ISSN-L)
- OpenAlex
- W2066339098
- Cited by
- 168
- References
- 20
- Citations by year
- 2025: 1 · 2024: 2 · 2023: 2 · 2022: 3 · 2021: 2 · 2020: 3 · 2019: 5 · 2018: 4 · 2017: 5 · 2016: 4 · 2015: 10 · 2014: 14 · 2013: 16 · 2012: 16
- FWCI
- 40.52
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- IEEE Micro (publishedVersion)
- UC Berkeley (submittedVersion)
- Funders
- National Science Foundation (0551739)
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Physical Sciences › Computer Science › Computer Networks and Communications › Distributed systems and fault tolerance
- Keywords
- ramps, open-source hardware, transactional memory, distributed systems, distributed shared memory, parallel computing
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