Understanding Metastability in SAR ADCs: Part II: Asynchronous
Abstract
This article is the second part of our tutorial on metastability in successive approximation register (SAR) analog-to-digital converters (ADCs). Having covered the synchronous topology in Part I in the Spring 2019 issue of IEEE Solid-State Circuits Magazine, we now investigate its asynchronous (or self-timed) counterpart. Even though the idea of successive approximation is rather old, it was not until 2006 that the benefits of asynchronous timing were unleashed through a seminal contribution by Chen et al. [1]. Since then, the asynchronous variant has emerged as a very popular option to achieve higher speeds and tame metastability issues more gracefully. The latter aspect is the focus of this article.
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Asynchronous time allocation reduces the data Code Error Rate compared with a synchronous counterpart of the same resolution, due to an exponential reduction in the probability of a metastability event.
“As shown in [10], this feature reduces the data Code Error Rate of the converter, CER, due to the exponential reduction, when compared with its synchronous counterpart of same resolution, in the probability of a metastability event occurring in the conversion of a sample, P meta .”
From A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS (2021) · cites this paper as [10]
In asynchronous SAR ADCs, the available conversion time is allocated to each comparison according to its difficulty, so more time can be used for harder comparisons.
“In consequence, more time can be employed in the harder comparisons.”
From A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS (2021) · cites this paper as [10]
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A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS
Campos, A. L., Navarro, J., Luppe, M., & de Lima, E. R. (2021) · Analog Integrated Circuits and Signal Processing · doi:10.1007/s10470-020-01742-6 · Cited by 8 · see citing works
- Authors
- Yu, A., Bankman, D., Zheng, K., & Murmann, B.
- Affiliations
- Massachusetts Institute of Technology (US)
- Stanford University (US)
- Venue
- IEEE Solid-State Circuits Magazine
- Published
- 2019
- Volume
- 11
- Issue
- 3
- Pages
- 16-32
- ISSN
- 1943-0582 (ISSN-L)
- 1943-0590
- OpenAlex
- W4242642979
- Cited by
- 28
- References
- 0
- Citations by year
- 2026: 1 · 2025: 5 · 2024: 6 · 2023: 4 · 2022: 5 · 2021: 4 · 2020: 3
- FWCI
- 1.06
- Type
- journal article
- Language
- en
- Open access
- closed
- Licence
- Locations
- IEEE Solid-State Circuits Magazine (publishedVersion)
- Topics
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in PLL and VCO Technologies
- Keywords
- metastability, successive approximation register ADC, asynchronous ADC, asynchronous circuits, analog-to-digital converter, high-speed ADC
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