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A Suggestion for a Fast Multiplier

Wallace, C. S.·1964·IEEE Transactions on Electronic Computers

Abstract

It is suggested that the economics of present large-scale scientific computers could benefit from a greater investment in hardware to mechanize multiplication and division than is now common. As a move in this direction, a design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step. Using straightforward diode-transistor logic, it appears presently possible to obtain products in under 1, μsec, and quotients in 3 μsec. A rapid square-root process is also outlined. Approximate component counts are given for the proposed design, and it is found that the cost of the unit would be about 10 per cent of the cost of a modern large-scale computer.

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Metadata

Authors
Wallace, C. S.
Venue
IEEE Transactions on Electronic Computers
Published
1964-02
Volume
EC-13
Issue
1
Pages
14-17
ISSN
0367-7508 (ISSN-L)
OpenAlex
W1983849809
Cited by
1,808
References
0
FWCI
3.36
Type
journal article
Language
en
Open access
closed

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CoChat. (2026). Citation check: A Suggestion for a Fast Multiplier. https://app.cochat.ai/papers/10.1109/pgec.1964.263830
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Wallace, C. S. (1964). A Suggestion for a Fast Multiplier. IEEE Transactions on Electronic Computers. https://doi.org/10.1109/pgec.1964.263830

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