The DOI matches its Crossref record; 11 of the 11 references it cites were found in a registry or an index.
A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration
Abstract
This paper presents a 12-GS/s 5-bit time-interleaved flash ADC realized in 65-nm CMOS. To improve the dynamic performance at high input frequencies, a statistics-based background calibration scheme for timing skew is employed. The timing skew is detected in the digital domain through a correlation-based algorithm and minimized by adjusting digitally controlled delay lines. In order to minimize power consumption, we employ near minimum size comparators, whose offset is reduced through foreground calibrated trim-DAC circuitry. With the timing calibration activated, the skew-related impairments are reduced by 12 dB at high input frequencies, resulting in an SNDR of 25.1 dB near Nyquist. The prototype IC consumes 81 mW from a 1.1 V supply, yielding a figure-of-merit of 0.35 pJ/conversion-step at low input frequencies, and 0.46 pJ/conversion-step for inputs near Nyquist.
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Citations
Cites
Matching properties of MOS transistors
Pelgrom, M. J. M., Duinmaijer, A. C. J., & Welbers, A. P. G. (1989) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.1989.572629 · Cited by 3,319
A Suggestion for a Fast Multiplier
Wallace, C. S. (1964) · IEEE Transactions on Electronic Computers · doi:10.1109/pgec.1964.263830 · Cited by 1,808
Splitting the unit delay [FIR/all pass filters design]
Laakso, T. I., Valimaki, V., Karjalainen, M., & Laine, U. K. (1996) · IEEE Signal Processing Magazine · doi:10.1109/79.482137 · Cited by 1,168
A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
Abo, A. M., & Gray, P. R. (1999) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.760369 · Cited by 923
Time interleaved converter arrays
Black, W. C., & Hodges, D. A. (1980) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.1980.1051512 · Cited by 828
Splitting the Unit Delay - Tools for fractional delay filter design
Laakso, T. I., Välimäki, V., Karjalainen, M., et al. (1996) · IEEE Signal Processing Magazine · Cited by 534
Jamal, S. M., Fu, D., Chang, N. C.-J., Hurst, P. J., & Lewis, S. H. (2002) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2002.804327 · Cited by 292
A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process
Van der Plas, G., Decoutere, S., & Donnay, S. (2006) · 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers · doi:10.1109/isscc.2006.1696294 · Cited by 229
The behaviour of flip-flops used as synchronizers and prediction of their failure rate
Veendrick, H. J. M. (1980) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.1980.1051359 · Cited by 228
Performance trends for analog to digital converters
Walden, R. H. (1999) · IEEE Communications Magazine · doi:10.1109/35.747256 · Cited by 153
Cited by
Stepanovic, D., & Nikolic, B. (2013) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2013.2239005 · Cited by 192
Mismatch Characterization of Small Metal Fringe Capacitors
Tripathi, V., & Murmann, B. (2014) · IEEE Transactions on Circuits and Systems I: Regular Papers · doi:10.1109/tcsi.2014.2332264 · Cited by 71
Self-citation
Metadata
- Authors
- El-Chammas, M., & Murmann, B.
- Venue
- IEEE Journal of Solid-State Circuits
- Published
- 2011-04
- Volume
- 46
- Issue
- 4
- Pages
- 838-847
- ISSN
- 0018-9200 (ISSN-L)
- 1558-173X
- OpenAlex
- W2137219772
- Cited by
- 264
- References
- 11
- FWCI
- 12.76
- Type
- journal article
- Language
- en
- Open access
- closed
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Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
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