The DOI matches its Crossref record; 2 of the 2 references it cites were found in a registry or an index.
On the Efficacy of a Fused CPU+GPU Processor (or APU) for Parallel Computing
Abstract
The graphics processing unit (GPU) has made significant strides as an accelerator in parallel computing. However, because the GPU has resided out on PCIe as a discrete device, the performance of GPU applications can be bottlenecked by data transfers between the CPU and GPU over PCIe. Emerging heterogeneous computing architectures that "fuse" the functionality of the CPU and GPU, e.g., AMD Fusion and Intel Knights Ferry, hold the promise of addressing the PCIe bottleneck. In this paper, we empirically characterize and analyze the efficacy of AMD Fusion, an architecture that combines general-purposex86 cores and programmable accelerator cores on the same silicon die. We characterize its performance via a set of micro-benchmarks (e.g., PCIe data transfer), kernel benchmarks(e.g., reduction), and actual applications (e.g., molecular dynamics). Depending on the benchmark, our results show that Fusion produces a 1.7 to 6.0-fold improvement in the data-transfer time, when compared to a discrete GPU. In turn, this improvement in data-transfer performance can significantly enhance application performance. For example, running a reduction benchmark on AMD Fusion with its mere 80 GPU cores improves performance by 3.5-fold over the discrete AMD Radeon HD 5870 GPU with its 1600 more powerful GPU cores.
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For applications where GPU memory bandwidth acts as a bottleneck, computational resources of GPUs remain underutilized.
“Similarly, for applications where the GPU memory bandwidth acts as a bottleneck [Daga et al. 2011;Spafford et al. 2012], the computational resources of GPUs remain underutilized.”
From A Survey of CPU-GPU Heterogeneous Computing Techniques (2015) · cites this paper as Daga et al. 2011
Citations
Cites
An algorithm for the machine calculation of complex Fourier series
Cooley, J. W., & Tukey, J. W. (1965) · Mathematics of Computation · doi:10.1090/s0025-5718-1965-0178586-1 · Cited by 13,154
Amdahl's Law in the Multicore Era
Hill, M. D., & Marty, M. R. (2008) · Computer · doi:10.1109/mc.2008.209 · Cited by 1,262
Flagged first, then by citations
Research works printed but not linked: 20
- 2011, APU 101: All about AMD Fusion Accelerated Processing Units, AMD
- volkov, 2008, Fitting FFT onto the G80 Architecture, University Of California Berkeley, 6
- 0, LAMMPS Molecular Dynamics Simulator
- 10.1145/1654059.1654090 · DOI
- 10.1016/j.jpdc.2008.05.011 · DOI · Paper page
- 10.1145/1356058.1356084 · DOI
- ryoo, 2008, Program Optimization Study on a 128-Core GPU, In Workshop on General Purpose Processing on Graphics Processing
- 10.1145/1513895.1513903 · DOI
- 10.1007/978-3-642-11950-7_21 · DOI
- bordawekar, 0, Can CPUs Match GPUs on Performance with Productivity?: Experiences with Optimizing a FLOP-intensive Application on CPUs and GPU, Research Report RC25033 IBM T J Watson Research Center
- vuduc, 2010, On the Limits of GPU Acceleration, In Proc USENIX Wkshp Hot Topics in Parallelism (HotPar)
- 10.1145/1735688.1735702 · DOI
- 10.1145/1815961.1816021 · DOI · Paper page
- 10.1145/1465482.1465560 · DOI · Paper page
- 2010, AMD Fusion Family of APUs: Enabling a Superior, Immersive PC Experience, AMD
- 0, The TOP500 Supercomputer Sites
- 10.1145/1186562.1015800 · DOI
- 10.1109/SC.2008.5214359 · DOI
- wong, 2010, Demystifying GPU Microarchitecture through Microbenchmarking, In ISPASS'10 Proceedings of the 37th IEEE International Symposium on Performance Analysis of Systems and Software
- 2010, NVIDIA GPUDirect Technology – Accelerating GPU-based Systems, Mellanox and NVIDIA
Cited by
Sorted by citations
A Survey of CPU-GPU Heterogeneous Computing Techniques
Mittal, S., & Vetter, J. S. (2015) · ACM Computing Surveys · doi:10.1145/2788396 · Cited by 568
iMLBench: A Machine Learning Benchmark Suite for CPU-GPU Integrated Architectures
Zhang, C., Zhang, F., Guo, X., He, B., Zhang, X., & Du, X. (2021) · IEEE Transactions on Parallel and Distributed Systems · doi:10.1109/tpds.2020.3046870 · Cited by 27
Metadata
- Authors
- Daga, M., Aji, A. M., & Feng, W.-C.
- Venue
- 2011 Symposium on Application Accelerators in High-Performance Computing
- Publisher
- IEEE
- Published
- 2011-07
- Pages
- 141-149
- Cited by
- 84
- References
- 2
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