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Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review

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Chaudhry, A., Kumar, M.J.·2004·IEEE Transactions on Device and Materials Reliability

Abstract

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

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Metadata

Authors
Chaudhry, A., & Kumar, M. J.
Venue
IEEE Transactions on Device and Materials Reliability
Published
2004-03
Volume
4
Issue
1
Pages
99-109
ISSN
1530-4388 (ISSN-L)
OpenAlex
W2096227378
Cited by
493
References
0
FWCI
9.48
Type
journal article
Language
en
Open access
green

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CoChat. (2026). Citation check: Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review. https://app.cochat.ai/papers/10.1109/tdmr.2004.824359
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Chaudhry, A., & Kumar, M. J. (2004). Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review. IEEE Transactions on Device and Materials Reliability. https://doi.org/10.1109/tdmr.2004.824359

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Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).

Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.