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Cited by 379

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Competitive learning with floating-gate circuits

Hsu, D., Figueroa, M., Diorio, C.·2002·IEEE Transactions on Neural Networks

Abstract

Competitive learning is a general technique for training clustering and classification networks. We have developed an 11-transistor silicon circuit, that we term an automaximizing bump circuit, that uses silicon physics to naturally implement a similarity computation, local adaptation, simultaneous adaptation and computation and nonvolatile storage. This circuit is an ideal building block for constructing competitive-learning networks. We illustrate the adaptive nature of the automaximizing bump in two ways. First, we demonstrate a silicon competitive-learning circuit that clusters one-dimensional (1-D) data. We then illustrate a general architecture based on the automaximizing bump circuit; we show the effectiveness of this architecture, via software simulation, on a general clustering task. We corroborate our analysis with experimental data from circuits fabricated in a 0.35-mum CMOS process.

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Metadata

Authors
Hsu, D., Figueroa, M., & Diorio, C.
Venue
IEEE Transactions on Neural Networks
Published
2002-05
Volume
13
Issue
3
Pages
732-744
ISSN
1045-9227 (ISSN-L)
OpenAlex
W2124583192
Cited by
379
References
2
FWCI
14.72
Type
journal article
Language
en
Open access
closed

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CoChat. (2026). Citation check: Competitive learning with floating-gate circuits. https://app.cochat.ai/papers/10.1109/tnn.2002.1000139
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Hsu, D., Figueroa, M., & Diorio, C. (2002). Competitive learning with floating-gate circuits. IEEE Transactions on Neural Networks. https://doi.org/10.1109/tnn.2002.1000139

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