HIPAcc: A Domain-Specific Language and Compiler for Image Processing

A Combined Corner and Edge Detector

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Liszt

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OptiML: An Implicitly Parallel Domain-Specific Language for Machine Learning

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Efficient Computation of Optical Flow Using the Census Transform

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A domain-specific approach to heterogeneous parallelism

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Shader algebra

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Whole-function vectorization

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Language virtualization for heterogeneous parallel computing

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Whole-function vectorization

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1 Intel’s Array Building Blocks: A Retargetable, Dynamic Compiler and Embedded Language

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Generating Device-specific GPU Code for Local Operators in Medical Imaging

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Code generation from a domain-specific language for C-based HLS of hardware accelerators

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Deriving Efficient Data Movement from Decoupled Access/Execute Specifications

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An experiment comparing Fortran programming times with the software physics hypothesis

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Code Generation for Embedded Heterogeneous Architectures on Android

Membarth, R., Reiche, O., Hannig, F., & Teich, J. (2016) · Cited by 26 · see citing works

A Generic Algorithm Template for Divide-and-Conquer in Multicore Systems

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A novel compilation approach for image processing graphs on a many-core platform with explicitly managed memory

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Generating GPU Code from a High-Level Representation for Image Processing Kernels

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Code generation for embedded heterogeneous architectures on android

Membarth, R., Reiche, O., Hannig, F., & Teich, J. (2014) · Design, Automation, and Test in Europe · doi:10.7873/date2014.099 · Cited by 13 · see citing works

High-performance SIMT code generation in an active visual effects library

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Towards Metaprogramming for Parallel Systems on a Chip

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A novel compilation approach for image processing graphs on a many-core platform with explicitly managed memory

Lepley, T., Paulin, P. G., & Flamand, É. (2013) · International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) · doi:10.1109/cases.2013.6662510 · Cited by 7 · see citing works

Effective Extensible Programming: Unleashing Julia on GPUs

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Spatial: a language and compiler for application accelerators

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HeteroCL

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Programming Heterogeneous Systems from an Image Processing DSL

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A survey on the practical use of UML for different software architecture viewpoints

Özkaya, M., & Erata, F. (2020) · Information and Software Technology · doi:10.1016/j.infsof.2020.106275 · Cited by 78 · see citing works

Parallel programming models for heterogeneous many-cores: a comprehensive survey

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Pushing the Level of Abstraction of Digital System Design: A Survey on How to Program FPGAs

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A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs

Chugh, N., Vasista, V., Purini, S., & Bondhugula, U. K. R. (2016) · International Conference on Parallel Architectures and Compilation Techniques (PACT) · doi:10.1145/2967938.2967969 · Cited by 46 · see citing works

AnyDSL: a partial evaluation framework for programming high-performance libraries

Leißa, R., Boesche, K., Hack, S., Pérard‐Gayot, A., Membarth, R., Slusallek, P., Müller, A., & Schmidt, B. (2018) · Proceedings of the ACM on Programming Languages · doi:10.1145/3276489 · Cited by 46 · see citing works

Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects

Lai, Y., Ustun, E., Xiang, S., Fang, Z., Rong, H., & Zhang, Z. (2021) · ACM Transactions on Reconfigurable Technology and Systems · doi:10.1145/3469660 · Cited by 45 · see citing works

The LEAP FPGA Operating System

Fleming, K. E., & Adler, M. (2016) · Springer eBooks · doi:10.1007/978-3-319-26408-0_14 · Cited by 43 · see citing works

Spatial: a language and compiler for application accelerators

Koeplinger, D., Feldman, M., Prabhakar, R., Zhang, Y., Hadjis, S., Fiszel, R., Zhao, T. Y., Nardi, L., Pedram, A., Kozyrakis, C., et al. (2018) · ACM SIGPLAN Notices · doi:10.1145/3296979.3192379 · Cited by 36 · see citing works

High-Level Synthesis for FPGAs—A Hardware Engineer’s Perspective

Lahti, S., & Hämäläinen, T. D. (2025) · IEEE Access · doi:10.1109/access.2025.3540320 · Cited by 32 · see citing works

ExaStencils: Advanced Multigrid Solver Generation

Lengauer, C., Apel, S., Bolten, M., Chiba, S., Rüde, U., Teich, J., Größlinger, A., Hannig, F., Köstler, H., Claus, L., et al. (2020) · Lecture notes in computational science and engineering · doi:10.1007/978-3-030-47956-5_14 · Cited by 32 · see citing works

From Loop Fusion to Kernel Fusion: A Domain-Specific Approach to Locality Optimization

Qiao, B., Reiche, O., Hannig, F., & Teich, J. (2019) · IEEE/ACM International Symposium on Code Generation and Optimization · doi:10.1109/cgo.2019.8661176 · Cited by 34 · see citing works

Software Architecture in Practice: Challenges and Opportunities

Wan, Z., Zhang, Y., Xia, X., Jiang, Y., & Lo, D. (2023) · Proceedings of the 31st ACM Joint European Software Engineering Conference and Symposium on the Foundations of Software Engineering · doi:10.1145/3611643.3616367 · Cited by 30 · see citing works

HiFlipVX: An Open Source High-Level Synthesis FPGA Library for Image Processing

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Generating FPGA-based image processing accelerators with Hipacc: (Invited paper)

Reiche, O., Özkan, M. A., Membarth, R., Teich, J., & Hannig, F. (2017) · International Conference on Computer Aided Design · doi:10.1109/iccad.2017.8203894 · Cited by 27 · see citing works

Shallow embedding of DSLs via online partial evaluation

Leißa, R., Boesche, K., Hack, S., Membarth, R., & Slusallek, P. (2015) · ACM SIGPLAN International Conference on Generative Programming: Concepts and Experiences (GPCE) · doi:10.1145/2814204.2814208 · Cited by 26 · see citing works

Automatic Kernel Fusion for Image Processing DSLs

Qiao, B., Reiche, O., Hannig, F., & Teich, J. (2018) · International Workshop on Software and Compilers for Embedded Systems (SCOPES) · doi:10.1145/3207719.3207723 · Cited by 24 · see citing works

FPGA-based accelerator design from a domain-specific language

Özkan, M. A., Reiche, O., Hannig, F., & Teich, J. (2016) · International Conference on Field Programmable Logic and Applications (FPL) · doi:10.1109/fpl.2016.7577357 · Cited by 24 · see citing works

A Safari through FPGA-based Neural Network Compilation and Design Automation Flows

Plagwitz, P., Hannig, F., Strobel, M., Strohmeyer, C., & Teich, J. (2021) · IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) · doi:10.1109/fccm51124.2021.00010 · Cited by 23 · see citing works

Schedule Synthesis for Halide Pipelines on GPUs

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Compiling high performance recursive filters

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Signals in the Cells: Multimodal and Contextualized Machine Learning Foundations for TherapeuticsPreprint

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Transpilers: A Systematic Mapping Review of Their Usage in Research and Industry

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Fuzzy-rough assisted refinement of image processing procedure for mammographic risk assessment

Qu, Y., Fu, Q., Shang, C., Deng, A., Reyer Zwiggelaar, A., George, M., & Shen, Q. (2020) · Applied Soft Computing · doi:10.1016/j.asoc.2020.106230 · Cited by 15 · see citing works

Optimizing memory bandwidth exploitation for OpenVX applications on embedded many-core accelerators

Tagliavini, G., Haugou, G., Marongiu, A., & Luca Benini, C. (2015) · Journal of Real-Time Image Processing · doi:10.1007/s11554-015-0544-0 · Cited by 13 · see citing works

Neda: Supporting Direct Inter-Core Neighbor Data Exchange in GPUs

Mahani, N., Sadrosadati, M., Falahati, H., Barkhordar, M., & Sarbazi‐Azad, H. (2018) · IEEE Computer Architecture Letters · doi:10.1109/lca.2018.2873679 · Cited by 13 · see citing works

BRASIL: A High-Integrity GPGPU Toolchain for Automotive Systems

Trompouki, M. M., & Kosmidis, L. (2019) · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · doi:10.1109/iccd46524.2019.00094 · Cited by 12 · see citing works

Performance Prediction of Multigrid-Solver Configurations

Grebhahn, A., Siegmund, N., Köstler, H., & Apel, S. (2016) · Lecture notes in computational science and engineering · doi:10.1007/978-3-319-40528-5_4 · Cited by 12 · see citing works

Programming tensor cores from an image processing DSL

Sioutas, S., Stuijk, S., Basten, T., Somers, L., & Corporaal, H. (2020) · International Workshop on Software and Compilers for Embedded Systems (SCOPES) · doi:10.1145/3378678.3391880 · Cited by 10 · see citing works

Loop Parallelization Techniques for FPGA Accelerator Synthesis

Reiche, O., Özkan, M. A., Hannig, F., Teich, J., & Schmid, M. (2017) · Journal of Signal Processing Systems · doi:10.1007/s11265-017-1229-7 · Cited by 10 · see citing works

Using high-level synthesis for rapid design of video processing pipes

Güzel, A. E., Levent, V. E., Tosun, M., Özkan, M. A., Akgün, T., Büyükaydın, D., Erbaş, C., & Uğurdağ, H. F. (2016) · IEEE East-West Design & Test Symposium (EWDTS) · doi:10.1109/ewdts.2016.7807644 · Cited by 9 · see citing works

Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs

Huff, D., Dai, S. X., & Hanrahan, P. (2021) · IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) · doi:10.1109/fccm51124.2021.00030 · Cited by 9 · see citing works

Auto-vectorization for image processing DSLs

Reiche, O., Kobylko, C., Hannig, F., & Teich, J. (2017) · ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES) · doi:10.1145/3078633.3081039 · Cited by 9 · see citing works

Toward Performance Portable Programming for Heterogeneous Systems on a Chip: A Case Study with Qualcomm Snapdragon SoC

Cabrera, A. M., Hitefield, S. D., Kim, J., Lee, S., Miniskar, N. R., & Vetter, J. S. (2021) · IEEE High Performance Extreme Computing Conference · doi:10.1109/hpec49654.2021.9622794 · Cited by 9 · see citing works

Systems of Partial Differential Equations in ExaSlang

Schmitt, C., Kuckuk, S., Hannig, F., Teich, J., Köstler, H., Rüde, U., & Lengauer, C. (2016) · Lecture notes in computational science and engineering · doi:10.1007/978-3-319-40528-5_3 · Cited by 8 · see citing works

Synthesis and optimization of image processing accelerators using domain knowledge

Reiche, O., Häublein, K., Reichenbach, M., Schmid, M., Hannig, F., Teich, J., & Fey, D. (2015) · Journal of Systems Architecture · doi:10.1016/j.sysarc.2015.09.004 · Cited by 8 · see citing works

Efficient Application of Tensor Core Units for Convolving Images

Groth, S., Teich, J., & Hannig, F. (2021) · International Workshop on Software and Compilers for Embedded Systems (SCOPES) · doi:10.1145/3493229.3493305 · Cited by 8 · see citing works

The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL

Qiao, B., Özkan, M. A., Teich, J., & Hannig, F. (2020) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1109/dac18072.2020.9218531 · Cited by 8 · see citing works

High-Level Synthesis for Hardware/Software Co-Design of Distributed Smart Camera Systems

Streit, F.-J., Letras, M., Schid, M., Falk, J., Wildermann, S., & Teich, J. (2017) · International Conference on Distributed Smart Cameras · doi:10.1145/3131885.3131932 · Cited by 7 · see citing works

Accurate and robust tracking of rigid objects in real time

Böttger, T., & Steger, C. T. (2020) · Journal of Real-Time Image Processing · doi:10.1007/s11554-020-00978-9 · Cited by 7 · see citing works

FLOWER: A comprehensive dataflow compiler for high-level synthesis

Amiri, P., Pérard‐Gayot, A., Membarth, R., Slusallek, P., Leißa, R., & Hack, S. (2021) · International Conference on Field-Programmable Technology (FPT) · doi:10.1109/icfpt52863.2021.9609930 · Cited by 7 · see citing works

Lightweight, generative variant exploration for high-performance graphics Applications

Selgrad, K., Lier, A., Köferl, F., Stamminger, M., & Lohmann, D. (2015) · ACM SIGPLAN International Conference on Generative Programming: Concepts and Experiences (GPCE) · doi:10.1145/2814204.2814220 · Cited by 6 · see citing works

Automatic Generation of Spatial Accelerator for Tensor Algebra

Jia, L., Luo, Z., Lu, L., & Liang, Y. E. (2022) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2022.3209949 · Cited by 6 · see citing works

GPotion: An embedded DSL for GPU programming in Elixir

Bois, A. R. D., & Cavalheiro, G. G. H. (2023) · doi:10.1145/3624309.3624314 · Cited by 6 · see citing works

ImageCL: An image processing language for performance portability on heterogeneous systems

Falch, T. L., & Elster, A. C. (2016) · International Conference on High Performance Computing & Simulation (HPCS) · doi:10.1109/hpcsim.2016.7568385 · Cited by 6 · see citing works

ImageCL: Language and source‐to‐source compiler for performance portability, load balancing, and scalability prediction on heterogeneous systems

Falch, T. L., & Elster, A. C. (2017) · Concurrency and Computation Practice and Experience · doi:10.1002/cpe.4384 · Cited by 6 · see citing works

Dataflow management, dynamic load balancing, and concurrent processing for real‐time embedded vision applications using Quasar

Goossens, B. (2018) · International Journal of Circuit Theory and Applications · doi:10.1002/cta.2494 · Cited by 6 · see citing works

RaTrace: simple and efficient abstractions for BVH ray traversal algorithms

Pérard‐Gayot, A., Weier, M., Membarth, R., Slusallek, P., Leißa, R., & Hack, S. (2017) · ACM SIGPLAN International Conference on Generative Programming: Concepts and Experiences (GPCE) · doi:10.1145/3136040.3136044 · Cited by 5 · see citing works

Let Coarse-Grained Resources Be Shared: Mapping Entire Neural Networks on FPGAs

Juang, T.-H., Schlaak, C., & Dubach, C. (2023) · ACM Transactions on Embedded Computing Systems · doi:10.1145/3609109 · Cited by 5 · see citing works

RaTrace: simple and efficient abstractions for BVH ray traversal algorithms

Pérard‐Gayot, A., Weier, M., Membarth, R., Slusallek, P., Leißa, R., & Hack, S. (2017) · ACM SIGPLAN Notices · doi:10.1145/3170492.3136044 · Cited by 5 · see citing works

A GPU optimization workflow for real-time execution of ultra-high frame rate computer vision applications

Nourazar, M., Booth, B. G., & Goossens, B. (2023) · Journal of Real-Time Image Processing · doi:10.1007/s11554-023-01384-7 · Cited by 5 · see citing works

Enabling OpenVX support in mW-scale parallel accelerators

Tagliavini, G., Haugou, G., Marongiu, A., & Luca Benini, C. (2016) · International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) · doi:10.1145/2968455.2968518 · Cited by 5 · see citing works

Hok: Higher-Order GPU kernels in Elixir

Bois, A. R. D., Perlin, T., Antunes, F. P., & Cavalheiro, G. G. H. (2024) · doi:10.5753/sblp.2024.3690 · Cited by 4 · see citing works

FAUPU - A design framework for the development of programmable image processing architectures

Reichenbach, M., Lieske, T., Vaas, S., Häublein, K., & Fey, D. (2015) · International Conference on ReConFigurable Computing and FPGAs (ReConFig) · doi:10.1109/reconfig.2015.7393309 · Cited by 4 · see citing works

Unveiling kernel concurrency in multiresolution filters on GPUs with an image processing DSL

Qiao, B., Reiche, O., Teich, J., & Hannig, F. (2020) · doi:10.1145/3366428.3380773 · Cited by 4 · see citing works

Transitioning Spiking Neural Network Simulators to Heterogeneous Hardware

Nguyen, Q. A. P., Andelfinger, P., Tan, W. J., Cai, W., & Knoll, A. (2021) · ACM Transactions on Modeling and Computer Simulation · doi:10.1145/3422389 · Cited by 4 · see citing works

RSFIN: A Rule Search-based Fuzzy Inference Network for performance prediction of configurable software systems

Li, Y., Bao, L., Huang, K., Wu, C. Q., & Li, X. (2023) · Journal of Systems and Software · doi:10.1016/j.jss.2023.111913 · Cited by 4 · see citing works

Task-DAG Support in Single-Source PHAST Library

Peccerillo, B., & Bartolini, S. (2019) · International Workshop on Programming Models and Applications for Multicores and Manycores (PMAM) · doi:10.1145/3303084.3309496 · Cited by 4 · see citing works

Bitwidth customization in image processing pipelines using interval analysis and SMT solvers

Purini, S., Benara, V., Choudhury, Z., & Bondhugula, U. K. R. (2020) · doi:10.1145/3377555.3377899 · Cited by 4 · see citing works

HipaccVX: wedding of OpenVX and DSL-based code generation

Özkan, M. A., Ok, B., Qiao, B., Teich, J., & Hannig, F. (2020) · Journal of Real-Time Image Processing · doi:10.1007/s11554-020-01015-5 · Cited by 4 · see citing works

SlidingConv: Domain-Specific Description of Sliding Discrete Cosine Transform Convolution for Halide

Kanetaka, Y., Takagi, H., Maeda, Y., & Fukushima, N. (2023) · IEEE Access · doi:10.1109/access.2023.3345660 · Cited by 3 · see citing works

Flow Driven GPGPU Programming combining Textual and Graphical Programming

Hoegg, T., Fiedler, G., Koehler, C., & Kolb, A. (2016) · International Workshop on Programming Models and Applications for Multicores and Manycores (PMAM) · doi:10.1145/2883404.2883412 · Cited by 3 · see citing works

Compiling Algorithms for Heterogeneous Systems

Bell, S., Pu, J., Hegarty, J., & Horowitz, M. (2018) · Synthesis lectures on computer architecture · doi:10.2200/s00816ed1v01y201711cac043 · Cited by 3 · see citing works

A High-Performance Image Processing DSL for Heterogeneous Architectures

Selgrad, K., Lier, A., Dörntlein, J., Reiche, O., & Stamminger, M. (2016) · doi:10.5555/3005729.3005734 · Cited by 3 · see citing works

Quasar, a high-level programming language and development environment for designing smart vision systems on embedded platforms

Goossens, B., Luong, H. Q., Aelterman, J., & Philips, W. R. (2018) · Design, Automation, and Test in Europe · doi:10.23919/date.2018.8342216 · Cited by 3 · see citing works

The HighPerMeshes framework for numerical algorithms on unstructured grids

Alhaddad, S., Förstner, J., Groth, S., Grünewald, D., Grynko, Y., Hannig, F., Kenter, T., Pfreundt, F., Plessl, C., Schotte, M., et al. (2021) · Concurrency and Computation Practice and Experience · doi:10.1002/cpe.6616 · Cited by 3 · see citing works

ReconOS

Agne, A., Platzner, M., Plessl, C., Happe, M., & Lübbers, E. (2016) · Springer eBooks · doi:10.1007/978-3-319-26408-0_13 · Cited by 3 · see citing works

Auto-vectorization for image processing DSLs

Reiche, O., Kobylko, C., Hannig, F., & Teich, J. (2017) · ACM SIGPLAN Notices · doi:10.1145/3140582.3081039 · Cited by 3 · see citing works

The Good, the Bad and the Ugly: Practices and Perspectives on Hardware Acceleration for Embedded Image Processing

Fryer, J., & Garcia, P. (2023) · Journal of Signal Processing Systems · doi:10.1007/s11265-023-01885-5 · Cited by 2 · see citing works

GPotion: Embedding GPU programming in Elixir

Bois, A. R. D., & Cavalheiro, G. G. H. (2025) · Journal of Computer Languages · doi:10.1016/j.cola.2025.101323 · Cited by 2 · see citing works

SkePU-DNN: Algorithmic Skeleton Programming for Deep Learning on Heterogeneous Systems

Qummar, S., Ernstsson, A., Keßler, C. W., & Sysoev, O. (2025) · IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum · doi:10.1109/ipdpsw66978.2025.00068 · Cited by 2 · see citing works

Rapid customization of image processors using Halide

Korhonen, V., Jääskeläinen, P., Koskela, M., Viitanen, T. T., & Takala, J. (2015) · IEEE Global Conference on Signal and Information Processing · doi:10.1109/globalsip.2015.7418272 · Cited by 2 · see citing works

Transitioning Spiking Neural Network Simulators to Heterogeneous Hardware

Nguyen, Q. A. P., Andelfinger, P., Cai, W., & Knoll, A. (2019) · ACM/IEEE/SCS Workshop on Principles of Advanced and Distributed Simulation (PADS) · doi:10.1145/3316480.3322893 · Cited by 2 · see citing works

Parallel Programming Models for Heterogeneous Many-Cores : A SurveyPreprint

Fang, J., Huang, C., Tang, T., & Wang, Z. (2020) · arXiv (Cornell University) · doi:10.48550/arxiv.2005.04094 · Cited by 2 · see citing works

swCUDA: Auto parallel code translation framework from CUDA to ATHREAD for new generation sunway supercomputer

Yu, M., Ma, G., Wang, Z., Tang, S., Chen, Y., Wang, Y., Liu, Y., Jia, D., & Wei, Z. (2024) · CCF Transactions on High Performance Computing · doi:10.1007/s42514-023-00159-7 · Cited by 1 · see citing works

Fast Generation of Custom Floating-Point Spatial Filters on FPGAs

Campos, N., Edirisinghe, E. A., Chesnokov, S., & Larkin, D. (2024) · IEEE Access · doi:10.1109/access.2024.3486066 · Cited by 1 · see citing works

Exploring data flow design and vectorization with oneAPI for streaming applications on CPU+GPU

Campos, C., Asenjo, R., & Navarro, A. G. (2025) · The Journal of Supercomputing · doi:10.1007/s11227-024-06891-3 · Cited by 1 · see citing works

Caasper: providing accessible FPGA-acceleration over the network

Morales, V. M., Brakni, Y., Horrein, P.-H., & Baghdadi, A. (2015) · International Workshop on Rapid System Prototyping (RSP) · doi:10.1109/rsp.2015.7416549 · Cited by 1 · see citing works

DSL-Based Acceleration of Automotive Environment Perception and Mapping Algorithms for Embedded CPUs, GPUs, and FPGAs

Fickenscher, J., Hannig, F., & Teich, J. (2019) · Lecture notes in computer science · doi:10.1007/978-3-030-18656-2_6 · Cited by 1 · see citing works

Effect of photo album service on the construction of network image resources in the wireless network environment

Meng, F. (2022) · Measurement · doi:10.1016/j.measurement.2022.111033 · Cited by 1 · see citing works

Underwater Image Processing and Target Detection Algorithm Based on Deep Learning

Zheng, Y., & Yang, Y. (2022) · Lecture notes on data engineering and communications technologies · doi:10.1007/978-3-031-05484-6_46 · Cited by 1 · see citing works

ArcvaVX: OpenVX Framework for Adaptive Reconfigurable Computer Vision Architectures

Kalms, L., Nickel, M., & Göhringer, D. (2023) · Lecture notes in computer science · doi:10.1007/978-3-031-42921-7_7 · Cited by 1 · see citing works

Efficient parallel reduction on GPUs with Hipacc

Qiao, B., Reiche, O., Özkan, M. A., Teich, J., & Hannig, F. (2020) · International Workshop on Software and Compilers for Embedded Systems (SCOPES) · doi:10.1145/3378678.3391885 · Cited by 1 · see citing works

Simplified High Level Parallelism Expression on Heterogeneous Systems through Data Partition Pattern Description

Wu, S., Dong, X., Chen, H., Wang, L., Wang, Q., & Zhu, Z. (2022) · The Computer Journal · doi:10.1093/comjnl/bxac017 · Cited by 1 · see citing works

Special issue on heterogeneous real-time image processing

Fey, D., & Hannig, F. (2018) · Journal of Real-Time Image Processing · doi:10.1007/s11554-018-0763-2 · Cited by 1 · see citing works

Highly Abstracted Video Processing Language Meets Multi-Grain Auto-Parallelization

Furuhashi, K., Noda, K., Ono, K., & Tsumura, T. (2016) · International Conference on Signal-Image Technology & Internet-Based Systems (SITIS) · doi:10.1109/sitis.2016.28

Model-Based System Design and Evaluation of Image Processing Architectures with SimTAny Framework

Deitsch, A., & Schneider, V. (2018) · Lecture notes in computer science · doi:10.1007/978-3-319-74947-1_29

A Study of Retrieval Methods of Multi-Dimensional Images in Different Domains

Garg, S. (2018) · International Journal of Advanced Computer Science and Applications · doi:10.14569/ijacsa.2018.091041

IML - An Image Manipulation Language

Vieira, C., & de Medeiros, S. Q. (2019) · doi:10.1145/3355378.3355382

An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning

Qiao, B., Teich, J., & Hannig, F. (2021) · IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum · doi:10.1109/ipdpsw52791.2021.00067

Digital Media Design for Dynamic Gesture Interaction with Image Processing

Xiong, X., & Hou, Y. (2022) · Journal of Electrical and Computer Engineering · doi:10.1155/2022/4056622

Domain specific language for finite element modeling and simulation

Feng, Y., Abell, J. A., Yang, H., Wang, H., & Jeremić, B. (2024) · Advances in Engineering Software · doi:10.1016/j.advengsoft.2024.103666

Metric-based fuzzy rough sets for brain tumor magnetic resonance imaging classification

Cui, M., Li, F., Yao, W., & Peng, G. (2025) · Hacettepe Journal of Mathematics and Statistics · doi:10.15672/hujms.1659064

JOSer: Just-In-Time Object Serialization for Heavy Java Serialization Workloads

Yang, C., Nie, P., Lin, Z., Wang, W., Yu, Q., Wan, C., Jiang, H., & Chen, Y. (2026) · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · doi:10.1145/3779212.3790179

Automatic Parallelization for Heterogeneous Embedded Systems

Diarra, R. (2019) · doi:10.70675/935f042dz0737z4200z8610z9dd73072a7a9

Generating FPGA-based image processing accelerators with Hipacc: (Invited paper)

Reiche, O., Özkan, M. A., Membarth, R., Teich, J., & Hannig, F. (2017) · International Conference on Computer Aided Design · doi:10.1109/iccad.2017.8203894 · Cited by 27 · see citing works

Generating FPGA-based image processing accelerators with Hipacc

Reiche, O., Özkan, M. A., Membarth, R., Teicha, J., & Hannig, F. (2017) · International Conference on Computer Aided Design · doi:10.5555/3199700.3199842 · Cited by 14 · see citing works

Code Generation from a Domain-specific Language for C-based HLS of Hardware Accelerators

(2016)

HIPAcc

Schmid, M., Reiche, O., Hannig, F., & Teich, J. (2016) · Springer eBooks · doi:10.1007/978-3-319-26408-0_12

A High-Performance Image Processing DSL for Heterogeneous Architectures

Selgrad, K., Lier, A., Dörntlein, J., Reiche, O., & Stamminger, M. (2016) · doi:10.5555/3005729.3005734 · Cited by 3 · see citing works