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Multilevel Inverter Topologies With Reduced Device Count: A Review

Gupta, Krishna Kumar, Ranjan, Alekh, Bhatnagar, Pallavee, Sahu, Lalit Kumar, Jain, Shailendra·2016·IEEE Transactions on Power Electronics

Abstract

Multilevel inverters have created a new wave of interest in industry and research. While the classical topologies have proved to be a viable alternative in a wide range of high-power medium-voltage applications, there has been an active interest in the evolution of newer topologies. Reduction in overall part count as compared to the classical topologies has been an important objective in the recently introduced topologies. In this paper, some of the recently proposed multilevel inverter topologies with reduced power switch count are reviewed and analyzed. The paper will serve as an introduction and an update to these topologies, both in terms of the qualitative and quantitative parameters. Also, it takes into account the challenges which arise when an attempt is made to reduce the device count. Based on a detailed comparison of these topologies as presented in this paper, appropriate multilevel solution can be arrived at for a given application.

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Metadata

Authors
Gupta, K. K., Ranjan, A., Bhatnagar, P., Sahu, L. K., & Jain, S.
Venue
IEEE Transactions on Power Electronics
Published
2016-01
Volume
31
Issue
1
Pages
135-151
ISSN
  • 0885-8993 (ISSN-L)
  • 1941-0107
OpenAlex
W1988224651
Cited by
1,193
References
0
FWCI
44.27
Type
journal article
Language
en
Open access
closed

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CoChat. (2026). Citation check: Multilevel Inverter Topologies With Reduced Device Count: A Review. https://app.cochat.ai/papers/10.1109/tpel.2015.2405012
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Gupta, K. K., Ranjan, A., Bhatnagar, P., Sahu, L. K., & Jain, S. (2016). Multilevel Inverter Topologies With Reduced Device Count: A Review. IEEE Transactions on Power Electronics. https://doi.org/10.1109/tpel.2015.2405012

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