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The DOI matches its Crossref record; 4 of the 4 references it cites were found in a registry or an index.

Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator

Open access
Neil, Daniel, Liu, Shih-Chii·2014·IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Abstract

Current neural networks are accumulating accolades for their performance on a variety of real-world computational tasks including recognition, classification, regression, and prediction, yet there are few scalable architectures that have emerged to address the challenges posed by their computation. This paper introduces Minitaur, an event-driven neural network accelerator, which is designed for low power and high performance. As an field-programmable gate array-based system, it can be integrated into existing robotics or it can offload computationally expensive neural network tasks from the CPU. The version presented here implements a spiking deep network which achieves 19 million postsynaptic currents per second on 1.5 W of power and supports up to 65 K neurons per board. The system records 92% accuracy on the MNIST handwritten digit classification and 71% accuracy on the 20 newsgroups classification data set. Due to its event-driven nature, it allows for trading off between accuracy and latency.

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Crossref · 10.1109/tvlsi.2013.2294916

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Metadata

Authors
Neil, D., & Liu, S.-C.
Venue
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Published
2014-12
Volume
22
Issue
12
Pages
2621-2628
ISSN
  • 1063-8210 (ISSN-L)
  • 1557-9999
OpenAlex
W2088192327
Cited by
268
References
4
FWCI
11.14
Type
journal article
Language
en
Open access
bronze

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CoChat. (2026). Citation check: Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator. https://app.cochat.ai/papers/10.1109/tvlsi.2013.2294916
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Neil, D., & Liu, S.-C. (2014). Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. https://doi.org/10.1109/tvlsi.2013.2294916

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