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Hybrid memory cube new DRAM architecture increases density and performance
Abstract
Multi-core processor performance is limited by memory system bandwidth. The Hybrid Memory Cube is a three-dimensional DRAM architecture that improves latency, bandwidth, power and density. Through-silicon vias (TSVs), 3D packaging and advanced CMOS performance enable a new approach to memory system architecture. Heterogeneous die are stacked with significantly more connections, thereby reducing the distance signals travel.
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Cited by
Efficient Processing of Deep Neural Networks: A Tutorial and Survey
Sze, V., Chen, Y.-H., Yang, T.-J., & Emer, J. S. (2017) · Proceedings of the IEEE · doi:10.1109/jproc.2017.2761740 · Cited by 4,215
“le of using eDRAM for DNN processing can be found in DaDianNao [89], which uses 36MB of eDRAM to store the weights for the fully-connected layers. 3-D memory, such as Micron’s Hyper Memory Cube (HMC) [94], stacks the DRAM on top of the logic using through silicon vias (TSV); this results in an order of magnitude highe…”
MethodAn overview of through-silicon-via technology and manufacturing challenges
Gambino, J. P., Adderly, S. A., & Knickerbocker, J. U. (2015) · Microelectronic Engineering · doi:10.1016/j.mee.2014.10.019 · Cited by 317
Deep Learning on Mobile and Embedded Devices: State-of-the-art, Challenges, and Future Directions
Chen, Y., Zheng, B., Zhang, Z., Wang, Q., Shen, C., & Zhang, Q. (2021) · ACM Computing Surveys · doi:10.1145/3398209 · Cited by 159
Data-Centric Computing Frontiers: A Survey On Processing-In-Memory
Siegl, P., Buchty, R., & Berekovic, M. (2016) · Proceedings of the Second International Symposium on Memory Systems · doi:10.1145/2989081.2989087 · Cited by 55
Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM
Seshadri, V., Lee, D., Mullins, T., Hassan, H., Boroumand, A., Kim, J., Kozuch, M. A., Mutlu, O., Gibbons, P. B., & Mowry, T. C. (2016) · arXiv · doi:10.48550/arxiv.1611.09988 · Cited by 54
Metadata
- Authors
- Jeddeloh, J., & Keeth, B.
- Venue
- 2012 Symposium on VLSI Technology (VLSIT)
- Publisher
- IEEE
- Published
- 2012-06
- Pages
- 87-88
- OpenAlex
- W1981220134
- Cited by
- 444
- References
- 0
- FWCI
- 38.48
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Jeddeloh, J., & Keeth, B. (2012). Hybrid memory cube new DRAM architecture increases density and performance. 2012 Symposium on VLSI Technology (VLSIT). https://doi.org/10.1109/vlsit.2012.6242474
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Bibliographic data: Semantic Scholar, OpenAlex, Crossref.
Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.
