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A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology

Heath, James R., Kuekes, Philip J., Snider, Gregory S., Williams, R. Stanley·1998·Science

Abstract

Teramac is a massively parallel experimental computer built at Hewlett-Packard Laboratories to investigate a wide range of different computational architectures. This machine contains about 220,000 hardware defects, any one of which could prove fatal to a conventional computer, and yet it operated 100 times faster than a high-end single-processor workstation for some of its configurations. The defect-tolerant architecture of Teramac, which incorporates a high communication bandwith that enables it to easily route around defects, has significant implications for any future nanometer-scale computational paradigm. It may be feasible to chemically synthesize individual electronic components with less than a 100 percent yield, assemble them into systems with appreciable uncertainty in their connectivity, and still create a powerful and reliable data communications network. Future nanoscale computers may consist of extremely large-configuration memories that are programmed for specific tasks by a tutor that locates and tags the defects in the system.

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Research works printed but not linked: 17

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Metadata

Authors
Heath, J. R., Kuekes, P. J., Snider, G. S., & Williams, R. S.
Venue
Science
Published
1998-06-12
Volume
280
Issue
5370
Pages
1716-1721
ISSN
  • 0036-8075 (ISSN-L)
  • 1095-9203
OpenAlex
W2022829874
Cited by
889
References
2
FWCI
38.86
Type
journal article
Language
en
Open access
closed

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Heath, J. R., Kuekes, P. J., Snider, G. S., & Williams, R. S. (1998). A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology. Science. https://doi.org/10.1126/science.280.5370.1716

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