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Cited by 580

The DOI matches its Crossref record; 3 of the 3 references it cites were found in a registry or an index.

Energy-aware mapping for tile-based NoC architectures under performance constraints

Hu, Jingcao, Marculescu, Radu·2003·Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC

Abstract

In this paper, we present an algorithm which automatically maps the IPs/cores onto a generic regular Network on Chip (NoC) architecture such that the total communication energy is minimized. At the same time, the performance of the mapped system is guaranteed to satisfy the specified constraints through bandwidth reservation. As the main contribution, we first formulate the problem of energy-aware mapping, in a topological sense, and then propose an efficient branch-and-bound algorithm to solve it. Experimental results show that the proposed algorithm is very fast and robust, and significant energy savings can be achieved. For instance, for a complex video/audio SoC design, on average, 60.4% energy savings have been observed compared to an ad-hoc implementation.

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Metadata

Authors
Hu, J., & Marculescu, R.
Venue
Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC
Publisher
ACM Press
Published
2003
Pages
233
OpenAlex
W2054302810
Cited by
580
References
3
Type
conference abstract
Language
en
Open access
closed

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CoChat. (2026). Citation check: Energy-aware mapping for tile-based NoC architectures under performance constraints. https://app.cochat.ai/papers/10.1145/1119772.1119818
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Hu, J., & Marculescu, R. (2003). Energy-aware mapping for tile-based NoC architectures under performance constraints. Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC. https://doi.org/10.1145/1119772.1119818

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